I. J. of Electrical & Electronics Research
Research Article | 
Analysis of Different Delay Lines in Terms of Propagation Delay, Area and Power Dissipation
Author(s): Harshada Deouskar and Nikhil Saxena
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 2,issue 4
Publisher : FOREX Publication
Published : 30 December 2014
e-ISSN : 2347-470X
Page(s) : 40-43
Abstract
In this paper, an analysis of different delay lines based on CMOS architecture has been done. Comparison has been made on these delay lines in terms of propagation delay, power dissipation, area, and power delay product. After the analysis of those performance parameters, the tradeoff has been made for better performance of delay lines.
Keywords: PDP, TDC, Propagation delay.
Harshada Deouskar*, Department of Electronics & Communicatio GITS, Gwalior India; Email: harshadadeouskar@gmail.com
Nikhil Saxena, Assistant Professor Department of Electronics & Communication ITM, Gwalior, India; Email: saxena.nikhil9@gmail.com
-
[1] Neil H. E. Weste, David Money Harris “CMOS VLSI Design A Circuits and Systems Perspective” Fourth Edition, 2011.
-
[2] Sung-Mo Kang, Yusuf Leblebigi “CMOS digital integrated circuits Analysis and Design” (second edition), 2003.
-
[3] Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic “Digital Integrated Circuits—A Design Perspective (2nd Ed), 2002.
-
[4] Yasuo Arai, Member, IEEE, and Masahiro Ikeno “A time digitiser CMOS gate array with a 250ps time resolution” in feb. 1996
-
[5] Jim stiles “Power delay product”, The University of Kansas 11-5-2004.