I. J. of Electrical & Electronics Research
Research Article | 
Review Paper on Placement Algorithms
Author(s): Mitali* and Deepak Bhati
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 4, Issue 2
Publisher : FOREX Publication
Published : 30 june 2016
e-ISSN : 2347-470X
Page(s) : 49-52
Abstract
Placement is a step considered after floor planning in FPGA flow in ASIC. It defines the location of logic cells within functional blocks and to minimize the routing length. We adjust the logic cells in this way so that minimum interconnect length, area and density are used. In this paper we will discuss some of methods of placement of logic cells.
Keywords: Placement Algorithms, FPGA.
Mitali*, Academic & Consultancy Services Division C-DAC, Mohali, India; Email: mitali.garg6@gmail.com
Deepak Bhati, Academic & Consultancy Services Division C-DAC, Mohali, India; Email: deepakbhati35@gmail.com
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[1] Q. Ma, E. F. Y. Young, and K. P. Pun, "Analog placement with common centroid constraints," Proc. ICCAD, 2007, pp. 579-585.
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[2] Min Pan, Chris Chu “IPR: An Integrated Placement and Routing Algorithm”, Proc. Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, San Diego, CA.
-
[3] Application-specific-integrated-circuits-MJ-smith.
-
[4] Hanan, M., P. K. Wolff Sr., and B. J. Agule. 1973. _Some experimental results on placement techniques._ In Proceedings of the 13th Design Automation Conference. Reference to complete graph wire measure.
-
[5] Hartoog, M. R., 1986. _Analysis of placement procedures for VLSI standard cell layout._ In Proceedings of the 23rd Design Automation Conference.