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Research Article |

Trade-off for Leakage Power Reduction in Deep Sub Micron SRAM Design

Author(s): Tripti Tripathi*, Dr. D. S. Chauhan and Dr. S. K. Singh

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 4, issue 4

Publisher : FOREX Publication

Published : 30 December 2016

e-ISSN : 2347-470X

Page(s) : 110-117

DOI: https://doi.org/10.37391/IJEER.040401

Abstract

Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power techniques used in 6T SRAM cell and their comparative study.

Keywords: CMOS, SRAM, SNM, DRV.




Tripti Tripathi*, Department of ECE Inderprastha Engineering College Uttar Pradesh, India; Email: tripti.tripathi@ipec.org.in

Dr. D. S. Chauhan, GLA University Mathura (U.P.), India; Email: pdschauhan@gmail.com

Dr. S. K. Singh, Department of Electronics and Communication VIET, Uttar Pradesh, India; Email: sanjaysinghraj@rediffmail.com

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Tripti Tripathi, Dr. D. S. Chauhan and Dr. S. K. Singh (2016), Trade-off for Leakage Power Reduction in Deep Sub Micron SRAM Design. IJEER 4(4), 110-117. DOI: 10.37391/IJEER.040401.