Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso

░ ABSTRACT - Reduction of Leakage power at nano meter regime has become a challenging factor for VLSI designers. This is owing to the need for low-power, battery-powered portable pads, high-end gadgets and various communication devices. Memories are made up of Static RAM and Dynamic RAM. SRAM has had a tremendous impact on the global VLSI industry and is preferred over DRAM because of its low read and write access time. This research study proposes a new method has been proposed of 6T Static Random Access Memory cell to decrease the leakage current at various technologies. Three source biasing methods are used to minimize the 6T SRAM cell leakage power. The three methods are NMOS diode clamping, PMOS diode clamping and NMOS-PMOS diode clamping at 45 nm and 90 nm technology nodes. This paper also emphasizes on the implementation of 6T SRAM cell using Multiple Threshold CMOS (MTCMOS) technique at 45nm technology. The simulation is achieved and various power dissipations are analyzed at supply voltage of 0.9 V and 0.45 V for 90 nm and 45 nm technology respectively using cadence virtuoso tool. PMOS clamping has shown the reduction in an average power by 82.19% than compared to other two proposed techniques.


░ 1. INTRODUCTION
In the past, performance and miniaturization of an integrated device was the major design concern of a VLSI designer. Technologies scaling from micro meter regime to nano meter regime yields in increased integration density referring to more number of semiconductor devices that are significantly smaller and quicker are embedded onto a single tiny piece of chip. This scaling is done to provide quicker speed and a greater operating frequency, resulting in increased power dissipation. With the growing popularity of portable battery-operated gadgets, power dissipation has become a crucial concern as these devices spend majority of the time in standby or sleep mode. Proper heat sinks are also necessary to dissipate the power in right manner in a circuit. Power dissipation also has an impact on packaging and reliability. Earlier days these battery-operated handheld gadgets had lower computing performances yielding to reduced power dissipation, while technology scaling led to higher performance than the non-portable devices. It is the need of an hour to prolong the life of the battery of these battery-operated portable gadgets and it's challenging for the circuit designers.
An Integrated Circuit is made up off combinational devices, sequential devices, memory units and input-output devices. Each circuit in an IC contributes to the total power dissipation. The portable battery-operated devices such as cell phones had a single core processor. With advancement in technology transistor density is increased with octa-core processors. Static RAM used in portable battery powered devices needs lower area and parallel lower power consumption [1]. Static RAM used in embedded controllers requires less read and write time. Due to the significant increase of lower power and lower voltage memory systems in recent years, SRAM has been emphasized in the research sector. On-chip memory is built utilizing arrays of tightly packed Static RAM cells to provide increased quality. As a memory cell, a 6T Static Random Access Memory (SRAM) is commonly utilized. The two most common kinds of power dissipation in an electronic circuit include Switching power and Static power dissipation. During the active mode of performance, when the device is under ON state, the power dissipation is majorly because of both switching power and static components of the semiconductor. While during the standby mode or sleep mode of operation, when the device is under OFF state, standby leakage current is responsible for the power dissipation. With technology scaling the leakage power is dominating that the dynamic power and hence is of major design concern to the VLSI designers as most of the portable devices are battery operated [2].

░ 2. MAJOR LEAKAGE CURRENT COMPONENTS
There are numerous origins of leakage current for nanometer devices, which includes low threshold voltage causes subthreshold leakage current, extremely thin gate oxides cause gate leakage current, and the heavily doped halo causes Band-To-Band Tunneling (BTBT). [3].

Sub-threshold Leakage Current
Subthreshold leakage occurs while the transistor is under weak inversion region of operation i.e. when gate to source potential of a semi-conductor is lesser than its threshold voltage i.e. < as well it is majorly comprised of diffusion current [4]. The two major subthreshold paths in 6T SRAM cell are from VDD to the GND and bitlines (BL, BLB) to the GND.

Gate Leakage Current
In the nanoscale era, excessive technology scaling amplifies Short Channel Effects (SCE) which includes ℎ roll-off and Drain Induced Barrier Leakage (DIBL). Each technological generation must scale the oxide thickness (Tox) to manage the SCE. Excessive miniaturization of Tox results in a large electric field, which leads to a large direct-tunneling current along the semiconductor's gate insulator [5]. Gate oxide tunneling current refers to the tunneling of electrons or holes through a semiconductor's gate oxide. The three important gate leakage processes in semiconductor device are tunneling in the Electron Conduction Band (ECB), Electron Valence Band (EVB), and Hole Valence Band (HVB). In ECB, electrons tunnel from the substrate's conduction band to the gate's conduction band and vice versa. In EVB, tunneling of electrons takes place from the substrate's valence band to the gate's conduction band. In HVB, holes tunnel from the substrate's valence band to the gate's valence band and vice versa.

Junction Leakage Current
The semiconductor Metal Oxide Semiconductor (MOS) device comprises of two PN junctions i.e. drain region to well and source region to well. PN junction leakage current occurs when these junctions are reverse biased. When 'P' and 'N' junctions are doped heavily results in BTBT tunneling while it also dominates PN junction leakage current [6]. Junction leakage is typically smaller than compared to other sources of leakage currents and it exists across the access transistors of SRAM cell [7].

░ 3. LEAKAGE CURRENT REDUCTION TECHNIQUES
Various leakage power reduction techniques have been proposed by researchers at the device, circuit, and architectural levels. At device level the leakage power is reduced by scaling the channel length, junction depth, oxide thickness [8][9][10]. Researchers have come up with newer transistor structure such as Fin-shaped FET (FINFET) having two or more gates resulting in lower short channel effect and lower subthreshold leakage current. At circuit level various leakage reduction techniques include DMOS, VTMOS, MTCMOS, STACKING (forced stack, sleep stack, lector, galore, sleepy keeper, and zigzag keeper), source biasing, body biasing, drain gating and many more [2]. At architectural level techniques include multiple modes management which puts the unutilized memory in sleep mode or standby mode thereby reducing leakage current which allows only a small part of the memory to be ON [11][12].

Body Biasing Scheme
The sub-threshold leakage current fluctuates exponentially as a function of device's threshold voltage ( ℎ ). This is adopted to decrease the propogation delay and leakage current to a greatly by varying the threshold voltage. Body bias alters the ℎ by applying the voltage across source and substrate terminal of a MOS device. The MOS transistor threshold voltage is related to source to substrate voltage as shown in Eq. (1) [13].
Where ℎ is the threshold potential of semiconductor device, is the threshold potential at zero body-bias, γ is the body effect factor, is the voltage across source and substrate and is the surface potential.
Reducing the voltage between source and substrate ( ), ℎ voltage of the device decreases thereby increasing the performance of a device. By increasing the potential across source and substrate ( ), ℎ of device increases thereby reducing the leakage current across OFF transistors [13].
In passive CMOS, the substrate terminal of PMOS is wired to VDD and substrate terminal of NMOS is wired to GND. Source to substrate (bulk) potential can be a non-zero value by adopting various body biasing schemes such as Forward Body Bias (FBB), Reverse Body Bias (RBB), DTMOS, VTMOS. Body biasing scales the threshold voltage of the device while supply voltage is kept constant. Body biasing either increases or decreases the ℎ of the device. The FBB enhances the performance (decreases the delay) by decreasing the ℎ of the device. The RBB minimizes the leakage current by boosting the ℎ of the device. Hence by smartly choosing both the delay and leakage current of the semiconductor can be decreased. The body bias can also characterized as fixed, variable and dynamic depending on the application [14]. A set forward or reverse bias voltage is placed across the transistor's substrate terminal in a Fixed Body Bias configuration. Different bias voltages are used in variable and dynamic body bias. Body bias voltages must be generated by an extra control circuitry called a Body Bias Generator in variable and dynamic body bias systems (BBG).

Source-biasing Scheme
Source biasing approach is employed to reduce leakage by utilizing an additional clamping circuitry in line with the pull down NMOS semiconductor to accomplish data retention. In between SRAM cell's source lines and GND, a high threshold voltage NMOS transistor is introduced. [15]. The gate terminal of NMOS transistor is latched to the WL (word line) as illustrated in Figure 5.
During the active mode, WL goes logic high which tunes ON NMOS transistor. The SRAM device functions conventionally since resistance is very small thereby the virtual ground (VSL) more or less functions as normal ground. During the standby mode, the WL goes low which turns OFF the NMOS transistor, results in decreasing the gate leakage and sub threshold leakage current. Drawback by using an extra NMOS transistor in the pull down network is that it increases dynamic energy, delay

Dynamic Threshold MOS (DTMOS)
Leakage reduction is attained by changing the threshold voltage ℎ of a device dynamically called as DTMOS. In this, the gate and substrate terminals are tied together [16]. Due to this configuration, threshold voltage is dynamically changed as the substrate voltage is varied with the input gate voltage VIN. Low ℎ is used in active mode, resulting in improved speed, whereas high ℎ is used in standby mode, resulting in lower static current. This technique makes use of multiple threshold voltages high and low threshold voltages ℎ to optimize power and delay as shown in figure 1. High threshold transistor switch slower thereby reduces the leakage power. While low threshold transistors switch faster but have high leakage power. MTCMOS makes use of high threshold voltage transistors known as sleep transistors. During the active mode of operation, these are ON and the circuit will behave normally. While in sleep mode, these transistors are OFF thereby reducing the leakage power [17]. These sleep transistors aims in reduction of standby leakage power to larger extent during the OFF state of SRAM cell

░ 4. CONVENTIONAL 6T SRAM CELL
Static RAM memory cells are made up of two inverters that are cross coupled as seen in Figure 2 [18]. The inverter2's output (Q') is connected to the inverte1's input (A). When the voltage transfer characteristics of the first inverter (VoA v/s ViA) are compared with those of the second inverter (VoB v/s ViB), three alternative operating locations (A, B, and C) are obtained. Because the loop gain is less than one, the operation points A and B are stable. Inverter one's output is high, while inverter two's output is low, as shown in point A. Inverter one's output is low, but inverter two's output is high, as seen in point B. The cell's three phases of operation are as mentioned below [19].
Read Operation: During this, bit lines (BL and BLB) act as output lines and both are pre-charged with certain voltage normally Vdd/2 (logic 1). When the word line is asserted, both the access transistors M5 and M6 linked to the bit lines are enabled, causing the bit-line voltages to decrease slightly. The output of these bit line voltages is send to sense amplifier which acts as an op amp comparator. It compares the difference between BL and BLB. If voltage across BL>BLB, it outputs a logic 1 and if voltage across BL<BLB, it outputs a logic 0. The advantage of using a sense amplifier is that it sets the output quickly without fully charging or discharging.
Write Operation: Bit lines act as input lines during the write process. The value that is to be written into the cell is provided by these bit lines. The word line will be asserted to logic high to access the bitlines i.e. WL=1. If logic 1 is to be written, bit line bar is loaded to supply rail VDD while bit line is discharged to low potential, and Word line is asserted, resulting in successful data (logic 1) writing into the cell. If logic 0 is to be written, BLB is discharged to ground potential, while BL is loaded to VDD and Word line is asserted, resulting in successful data (logic 0) writing into the cell.

International Journal of Electrical and Electronics Research (IJEER)
Open Access | Rapid and quality publishing Research Article | Volume 10, Issue 2 | Pages 341-346 | e-ISSN: 2347-470X Hold Operation: During the hold or ideal state, the word line is not connected i.e. WL=0 which does not turn on the access cells M5 and M6. This open circuits the cross coupled inverter from the bit lines (BL, BLB) and thereby the data is held in the memory cell. Hence is it said to be in hold state or ideal state as data is held in the latch mode. As long as the semiconductor is connected to the power source, it will continue to store the data.  By adding an extra high ℎ NMOS transistor between the SRAM cell's source line and Ground (GND), leakage current across a 6T SRAM cell is considerably decreased. During active state, word line is activated (WL=1) which turns ON the NMOS transistor and the SRAM cell behaves normally, since the resistance is smaller across the circuit. During the standby state, word line is deactivated (WL=0) which turns OFF the NMOS transistor thereby the source line ( ) will be raised to greater potential that results in decreasing the subthreshold leakage current and gate leakage.  A pair of NMOS and PMOS high threshold voltage transistors inserted in parallel between the source terminal and ground terminal of SRAM cell is as depicted in figure 7. The transient analysis of 6T SRAM device is as shown in figure 8. The test schematic where the voltages are applied the inputs WL, BL and BLB is as available in figure 9. The symbol of 6T SRAM cell which is generated from the schematic is as shown in figure 10.  Multiple Threshold CMOS (MTCMOS) of 6T SRAM cell is as given in figure 11. Two additional high ℎ transistors known as sleep transistors are used. A high ℎ PMOS cell is added across the PUN and supply voltage and a high ℎ NMOS cell is placed across the PDN & ground terminal. MTCMOS makes use of two threshold voltages in a circuit to obtain higher performance and lower leakage. During the active mode, these high ℎ sleep transistors are turned ON and low ℎ SRAM cell operates normally with small propagation delay. During the standby (Sleep) mode, these high ℎ sleep devices are turned OFF while the conduction path that may arise from low ℎ SRAM device is smartly cutoff thereby reducing the leakage current.