Performance Analysis of

Semi-Classical


░ 1. INTRODUCTION
Energy efficient and high-speed non-volatile memory is very important key aspect of developing the non-volatile computing devices for Internet of Thing (IoT) application. The IoT is a novel field of innovation that is rapidly gaining as advances in computing, storage devices and wireless and communication technology. The basic concepts of IoT is pervasive presence around us through different sensors, devices, actuators, smart phones etc. These are able to interact with each other and communicate their neighbors to reach common goals. IoT is fastest growing market which is expected to connect 50 billion things by 2025[Nokia] and grow $3.7 billion market. IoT is promising market of like home automation, automatic agriculture, smarter heat care, smarter natural disaster management and ultimately smarter world. As it has many applications and future market business but it has many challenges. IoT architecture consists of processing unit, wireless module and power storage. Already wireless technology achieved very improvement for last decade. Presently researchers focuses to resolve the issue related charge storage battery because for IoT wire based supply deployment is not feasible. So high-capacity storage battery requirement to power up the IoT devices for month or year based on application like month for home automation application and years for satellite or space application of IoT devices.
Due to technological advances, the efficiency of microprocessors has greatly improved and therefore a drastic processor speed increase has been observed in recent years. However, the memory speed has not been significantly increased and therefore a gap between processor performance and memory increases over time. To reduce the gap between microprocessor and memory performance, in the chip assembly memory is used by the silicon industry to reduce data extraction time. To improve system performance, SRAM density has been increased by device scaling by the researchers. Nowadays, SRAM devices have stable and high processing speed that is used in cache memory. For the design of SRAM cell two aspects are more important. The first is improved stability and second is smaller cell area. The number of transistors is increase day by day [1], resulting in an increase in the delay. The performance of transistor gets suffers a low threshold voltage, however, an increase the transistor of threshold voltage, which leads to an enhanced the Website: www.ijeer.forexjournal.co.in Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm Pressure Estimation with Photoplethysmography Signals and Semi-Classical Signal Analysis cell leakage and has an impact on the cell stability [2]. The objective of the researcher is reducing the delay of the SRAM by keeping performance. The cell area has been reduced by 30-50%. However, this area advantage will go down in future scaled down memory requiring reduced supply voltage. In comparison to the various 9T SRAM CMOS technology at different scaling node offers all data isolation by the bit lines of the memory cell, preventing sneak path, enabling higher data read and write stability, as well as lower leakage power. The SRAM cell of 9T is analyzed and carried out for its several parameters such as delay, power, voltage and temperature [3][4][5]. The CMOS based SRAM cell design having less power consumption. According to Moore's law, the transistor is doubled on the chip every two years due to decreasing of transistor size. As a results, the chip density increases while the device size decrease. For ultra-low-power applications, low power dissipation is a critical design issue. Leakage power has become a prominent factor of total power dissipation as technology advances. Voltage scaling is an effective technique to reduce the power dissipation of SRAM cell [6]. Demands of electrical vehicles increases day by day and to full fill the demands the manufactures require to produce more vehicles with in time. The functions of these vehicles are mainly controlled by the programmed ICs (Integrated Circuits) which require storage capacity to store the instructions. During last one year the automobile industry also faces chip crisis, due this the production of vehicles affected badly. OEM is a real manufacturer of vehicle parts that are fully compatible with the vehicle and manufactured with the same quality. We focus on the various designs of ultra-low power, durable logic circuits under process variation that decrease dynamic and static power consumption of 9T SRAM bit cells to a bare minimum. The memory technologies have seen advances in no-volatile memory such as ferromagnetic RAM (Fe-RAM), Phase change RAM (PCRAM), Resistive RAM (RRAM) and STT-MRAM (Spintransfer torque magnetic random-access memory).

░ 2. SYSTEM MODEL
In logic circuitry, an SRAM cell is having two stable states '0' or '1' and it is a semiconductor memory device for data storage. SRAM memory cells are organized in a matrix and can be individually addressed. The data read all the content with help of column decoder and stored in the SRAM cells. When a single bit line is connected to the drain terminal of a pass transistor, the noise margin tolerance capability is improved. During SRAM cell operation, control the stability, the bit line will pass through two input nodes of access transistor [7]. In the SRAM cell, the word line is responsible to enable the access transistor. The role of the bit line is transfer data of read and writes operation. There is no need for refreshing circuit in the SRAM cell [8]. An ideally SRAM cell is designed to be balanced device physically and electrically is perfectly between the two inverters.  has added an additional two access pass transistors (TN5 and TN6) for the bit line in the 6T SRAM cell and one access pass transistor (TN7) used for the read operation. The data is depending on node Q and QB and stored information by the access pass transistor TN3 or TN4. Singh et al. [9], discussed the comparative analysis of 9T SRAM proposed and existing SRAM design at 45nm technology. The group calculated the PDP with 36% improvement. In the SRAM structure are controlled by separate device of the read and write operation. For the read operation, the read word line (RWL) decide the transition. During the write operation, controls the transition by the access pass transistor NM3 and NM4 for column based write word-line (WWL). The two-stacked read port is enabled by the row-based high RWL and GND, and if QB = '1', the RBL is discharged, and sensing of Q = '0' is done by the sense amplifier. The reverse operation is used to read '1'. RBL is precharged by the VDD and WWL at low ('0'V). The crosscoupled inverter is separated from the outer interconnect, when WWL, WBL and WBLB is kept LOW and the latch is no intrusion effect [10]. RBL is discharge and remain at VDD at depend on the data in the cross coupled inverter. As a result, the read data from latch indirectly worked by the reading stack. Read circuitry is disabled to execute the writing operation by keeping RWL at LOW level when WWL is asserted. After asserting the WWL, the data is loaded by the WBL and WBLB and the write operation is begun by precharging. After the write bit lines are pre-charged, the access pass transistors NM3 and NM4 are turn on by asserting the WWL signal, allowing the data to be accessed or passed from the word bit line to the cell as shown in figure 3. As a result, data is stored into the cell at the appropriate nodes. Mishra et al. [33] recently designed SRAM cell of 9T, which consist of a single read bit line which consists of 2T read port and one tail transistor for low power and high stability as depicted Fig.3. When compared to a simple 6T SRAM cell developed at the same technology, the proposed design has a 22% reduction in static power dissipation. Also compared to 6T SRAM cell and ultralow voltage 9T SRAM cell, it improves write stability by 42% and 34% respectively. Author discussed the read write operating mode at various signal as shown in

Static Noise Margin (SNM)
The least possible DC noise voltage need to change the characteristics of the storage node is defined as static noise margin. In the SRAM cell, the sub-threshold voltage and channel length of the transistor have an exponential relationship. To preserve the SRAM cell strength at scaled technologies, the threshold voltage reduces with reduction in channel length [24,25].

Read Static Noise Margin (RSNM)
The RSNM is calculated from the cell stability to read the saved data. Due to of the scaling of critical current in scaled technology nodes, the read current is interrupted when the saved data change repeatedly. If increase the voltage also increases the SNM during read operation [25]. In 9T SRAM cell the values of RSNM is decreases due to decrease the technology as indicated in figure 6(a). The lowest value of RSNM is 170.2mV at 14nm technology.

Write Static Noise Margin (WSNM)
There are several topologies to enhance the WSNM value reported in literature [26,27]. The WSNM can be improved by reducing the supply voltage or increase the virtual ground  [28]. The WSNM of the SRAM cell is calculated using the butterfly curve [29]. The WSNM is 42% enhance against the conventional 9T SRAM cell [33].

Read and Write Access Time
The delay in SRAM cells is divided into two types: read and write access time. Read access time is the time that is required for data from storage node to appear on both bit-lines, while write access time is the time that is required for data from the write driver circuit to appear on the storage nodes of the cell. Normally, the W/L ratio of the transistor and the supply voltage determine the delay in an SRAM cell. After comparing it is observed that the read and write access time of 9T SRAM cell is improved. Figure 5(a) depicts the write access time for the topologies considered at various supply voltages. It is noted that the write access time is decreases after increase the supply voltage. In case of technology decrease the write access time increases as shown in figure 6(b).

Read/ Write energy
One of the most important parameter used to describe the performance of a device or system is energy. The read/write energy of the 9T SRAM cell is displayed in figure 5(b) after increase the supply voltage. In figure 5(b) it is shown that the read energy values is increase after increase the supply voltage and also write energy value is firstly decrease up to 0.7 V after that it increases.

Area Comparison
The layout of the 9T SRAM cells are design based on CMOS design rule in ref. [36,37]. The area for several of 9T SRAM cell is mention in the ref. [36,37]. The layout is depend on the width of pull-up and pull-down transistor in the SRAM cell.

░ 4. RESULT DISCUSSION OF EXISTING 9T SRAM
The performance of improvement as compared with existing work at various CMOS technology is shown in

░ 5. CONCLUSION
This review has focused on the 9T SRAM cell using CMOS technology relevance for the storing data. The comparisons of 9T SRAM have been discussed by various CMOS technology (180nm, 90nm, 65nm, 45nm, 32nm, 14nm). 9T SRAM cell were analyzed taking into account various performance parameters like propagation delay, read/write SNM, read/write energy, read/write access time etc. with an aim to develop the understanding required for better performance. Different approaches, strategies have been displayed including incorporation of different technology, their cross coupled CMOS inverter and access pass transistor. The existing structure of 9T SRAM cell have their advantage as well as disadvantage and hence the way towards designing better performing SRAM is still a challenges and thus it can be seen as an area hosting immense opportunities for research. The constancy of 9T SRAM cell of all performance parameter is discussed in the form of tabulated. As a result of the thorough survey and comparison study conducted in this research, it can be stated that an SRAM cell can be constructed to be more potent by improving the trade-off between different performance parameters. In the future work, we will design a reversible logic gate based 9T SRAM cell having the better performance and low power consumption as compare to the existing 9T SRAM cell discussed in this review paper. The reversible logic gate will use in the row decoder and column decoder to reduce the power consumption.