A Solution to VLSI: Digital Circuits Design in Quantum Dot Cellular Automata Technology

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░ 1. INTRODUCTION
Quantum Dot Cellular Automata (QCA), Resonant Tunneling Devices (RTD), Single Electron Transistors (SET), Tunneling Phase Logic (TPL), Carbon Nano Tube Transistors (CNT) are Nanodevices given by International Technology Roadmap for Semiconductors (ITRS). The best nanotechnology device among all these Nanodevices is QCA. It overcomes the drawbacks of CMOS technology [2]. QCA is transistor-less and efficient technology. It has high device density and low power consumption. It operates at Terahertz (THz) range. In QCA information is transferred by columbic repulsion and in CMOS technology current switching takes place.
The workflow shows the basics of QCA in section II. Different design layouts of XOR gates are given in section III and multiplexers are investigated and compared in section IV. Section V gives simulation software used in designing QCA circuits is described. It is used to compute the various parameters in the design. Section VI illustrates the experimentation for the implementation of a novel gate to achieve efficient circuit design in the field of nanotechnology. One such novel NOT gate with the best parameters achieved is elaborated. Section VII states the scope to design digital circuits towards digitalization in the field of QCA and the concluding remark which gives ideas for new researchers in the future for miniaturizing processors in an embedded system.

QCA Cells
QCA is formed by the term's quantum dot and cellular automata. Quantum dots are nanometer-scaled devices containing tiny droplets of free electrons. These dots are in the range of 2nm-10nm and are constructed from Aluminum using electron beam lithography techniques. Cellular automata consist of grid of cells. Four quantum dots are present at the four corners of the cell. Cells have a finite number of states at a discrete time. Cell state can be found by using its previous state and its immediate adjacent cells. When the cells are charged with two additional electrons, due to columbic repulsion between electrons they take either of the two opposite positions of the quantum dots. The placement of the electrons gives two possible states of cells that are termed cell polarizations or states of cells. These two possibilities are represented with two binary numbers i.e., 0 and 1. Thus the cell encodes the data as binary '0' and binary '1'. The cell structure is shown in figure 1 and figure 2 shows the states of a cell.    One of the main components in QCA is a MG gate. As per the name, majority gate, it always gives the output for the majority of the input combinations. It has five cells in which three of them are input cells, one is device cell and one cell is the output cell (F). Device cell is placed at the center of the gate and it decides the output based on the inputs. MG gate is as shown in 5. Figure shows if a,b,c as the inputs then the logical function of a MG gate is M(a,b,c) = ab+bc+ac. Using MG, AND gate and OR gate can be implemented by giving one of the inputs of MG as either polarized to -1 or +1. If the input C is polarized with +1, MG gate can be used as OR gate and used as AND gate if input C is polarized with -1.

Crossovers in QCA
Different wire crossovers in QCA are coplanar crossover, Signal Distribution Network and Multilayer crossover. Each crossover has its own advantages and disadvantages. Coplanar crossover uses both 90 0 and 45 0 QCA wires which results in the possibility of cross-coupling [6]. Also, the coplanar crossover has very less excitation energy which leads to stray charges and temperature effects [7]. These problems can be resolved with SDN (Signal Distribution network) which relies on nearestneighbor interactions which help in the rise of excitation energy, improvement in thermal effects. Multilayer crossover increases the complexity and cost of fabrication but can give the best device package density.

QCA Clocking
QCA clocking is different from the CMOS clock. CMOS uses a clock to control the timing. In QCA, the clock is used to direct the flow of data [6] i.e., switching and providing power gain to the circuits. In QCA, a clock is required for sequential circuits as well as combinational circuits. The electric field is used to generate Clock signals. Basically, the clock can be a continuous clocking or a zone clock. Continuous clocking creates metastability problems and so adiabatic clocking is used. Researchers have used different clocking schemes like, 1D, 2D, and 2D wave clocking schemes [6] to design and improve the speed parameter of the different digital circuits.
Zone clocking with four phases is used in a QCA Designer tool. Switch, Hold, Release and Relax are the four phases as shown in figure 6(a) [6]. Figure 6(b) [5] indicates the representation of clock zone signals. The switch phase determines the state of the cell according to adjacent cells [6] and is an important phase.
Each clocking zone has a phase shift of 90 0 .

░ 3. METHODOLOGY USED FOR XOR CIRCUITS
Designing digital circuits in QCA is of much attention in recent eras to achieve better performance metrics. Researchers have designed and proposed many XOR gate implementations. Table  1 gives the different designs implemented along with the parameters in consideration. Table 1 shows performance parameters such as the number of cells, total area in µm2, and delay. Designs are considered with different methodologies used.
Moustafa A et al [4] have prepared a basic building block of 27 cells using MG and NOT gate. Out of 27 cells, they used 11 cells as configuration cells. These cells can be customized as per the design need. M. R. Beigh et al presented the layouts with fewer crossovers and less cell count compared to previous designs [9]. S. Santra and U. Roy [10], proposed the XOR gate implementation with Boolean expression and by using basic gates which reduces cell count compared to previous designs. Authors in the paper [11] presented the XOR gate layout with proper arrangement of cells and clock delay. From these, we can say that, it's the modification in the Boolean expression of the XOR gate, the basic gates used to implement the XOR gate, the clocking scheme used and the number of crossovers used, etc. to design an XOR gate. If the number of cells required to implement a gate is less it automatically reduces the space requirement and improves the device density. The delay column indicates the number of clock phases the gate takes to give the output from the input. A value of 0.5 indicates that the output is delayed just by 1 clock phase and a value of 1 indicates that the output is delayed by 4 clock phases or 1 complete clock cycle.
The star mark indicates that this XOR gate implementation has less space requirement due to just 8 cells 0.006µm2 area and 0.5 delay giving maximum speed compared to all other implementations. Section IV elaborates on the software used for these circuit implementations and the performance parameters to be set during the layout and simulation.
░  Figure 7 shows the representation of variation in the number of cells. Figure 8 shows the area utilized in the design of XOR gates whereas figure 9 indicates the delay encountered in getting the output.   XOR gate implementation in QCADesigner is illustrated with results for two of the layouts in the following section. First, the layout is to be drawn in QCADesigner and then it is to be saved with extension .qca . In order to get the layout in the form of image format save the file with an extension .eps [23]. The simulation results once observed can also be saved with the same .eps extension to get it in image format. To view .eps image make use of Corel Draw software or Adobe Illustrator. For comparative analysis refer to figure 10 and figure 11 for the design mentioned in [13], figure 12 and figure 13 for the design mentioned in [22]. The layout of the XOR gate and its simulation from these two references is considered.
Observations from the layout show that the number of cells in figure 13 is very less, which is 8 whereas in figure 10, the number of cells is 36 and so the area requirement also, is observable. The simulation result indicates the difference in delay in achieving the output. Delay is more in the simulation indicated in figure 11 compared with the simulation in figure  13.

░ 4. METHODOLOGY USED FOR MULTIPLEXER CIRCUITS
Multiplexer or Mux has many applications in digital circuits and hence in any embedded system circuits. Also, in the near future, it will be used in digital Nano communications for signal encoding [24]. Researchers Table 2 shows that a 2:1 multiplexer circuit is designed with 3 MGs and a 4:1 Multiplexer circuit is designed using 9 MGs. The number of clocking zones required for 2:1 mux is 3 and for 4:1 it is 4. This table also shows the minimum number of QCA cells and the area used by cells in layout implementation. This clears the idea of further need in optimization to achieve miniaturization in the mux circuit and ultimately towards the application building using Mux. This further optimization requires different methodologies to be designed by researchers and will lead to optimized revolution in the field of Nanotechnology.  In the design of the multiplexer circuit, the authors have arranged cells as per the Boolean expression reduction technique with a common way of clock. The design of 2:1 mux in [25] has used a layout generator tool which is more complex and requires more area. S. Hashemi, M. R et al have presented the design of a 2:1 mux using a single and multilayer structure [26]. Cells need to be arranged in a way that leads to reduction in complexity, cell area and ultimately total area of the circuit layout. Figure 14 shows the layout of the 2:1 mux and its simulation result in figure 15.  This is an efficient 2:1 multiplexer. It gives the best results in comparison to previously completed work. It uses only nice cells. This is implemented using a cell interaction method and a single majority voter gate to achieve efficient performance parameters. It makes use of only 9 cells. The polarization achieved is +0.953 and -0.933.

░ 6. EXPERIMENTATION
This section gives the novel NOT gate design which can be used in building different circuits efficiently in the field of nanotechnology using QCA. Figure 18a shows a NOT gate with only 5 cells with a total area equal to 5814 nm 2 using normal cells. This gate provides an output polarization of 9.84 as depicted in figure 18b. This is one of the best gates in comparison with standard NOT gates in terms of best polarization and the number of cell count and hence total size. Standard NOT gate with fork shape has 9 cells, polarization of 9.51 with an area of 7198 nm 2. Thus, this novel gate provides an improvement of 55% in the number of cells, polarization raised by 0.33, and an 80.77% improvement in total area with respect to the fork shaped NOT gate.  An inverter with two cells is area efficient but is not robust and the polarization achieved is also very poor. Table 6 concludes that the standard NOT gate with fork shape is robust but it requires 9 cells with an area of 7198nm 2 and a polarization of 0.951. The proposed inverter is the best in comparison with the rest of the inverters. It gives the best results in the number of cell counts, total area and polarization. This inverter is possible with proper cell arrangement methodology.

Analysis
The analysis shows that the output is an inversion of the input. This inversion is due to the arrangement of cells to achieve more stability and their potential energy at the minimum level. Cell size is assumed as 18x18 nm and the separation between the neighbor cells is 2nm. As shown in figures 19 (a) and 19 (b), the square represents the QCA cell and the position of electrons inside that cell is represented by the filled circles.
To calculate the potential energy between two electron charges equation 2 is used. In this equation, U is the potential energy, k is the Boltz constant (9 x10 9 ), q1 and q2 are charges of electrons (1.602 x 10 -19 ) and r represents the distance between two electric charges [28][29]. If logic '0' is applied at the input side to cell 1, then cell 2, cell 3 and cell 4 will follow the opposite logic of input due to crosssection to cell 1. Let us find the position of electrons in the output cell. The potential energy at cell 5 is calculated with the state (a) and state (b) as shown in Figure 19(a) and 19b respectively. The one which gives minimum potential energy is the most stable state. Figure 19 (a) the potential energy of electron 'X' of cell 5 with respect to X1, X2, X3, X4 and Y1, Y2, Y3, Y4 of cells 1, 2, 3 and 4 is calculated. Similarly, the potential energy of electron 'Y' of cell 5 with respect to X1, X2, X3, X4 and Y1, Y2, Y3, Y4 of cells 1, 2, 3 and 4 is calculated. The total potential energy of electron 'X' with respect to all other cells is added using equation 4 to get 11 and the potential energy of electron 'Y' with respect to all other cells is added using equation 4 to get 12 . Total energy UT1 for 19(a) representation is the addition of 11 and 12 . This is indicated in Assumption 1. In a similar way, assumption 2 shows total energy UT1 for 19(b).

As indicated in
The analysis shows that the potential energy of cell 5 in figure  19(b) is lower. So, cell 5 is at logic '1'. It shows the inversion of input at the output. Similarly, if cell 1 is at logic '1', cell 5 will give logic '0'.

░ 7. CONCLUSION AND FUTURE SCOPE
8 cells and 0.006 μm2 area and delay of just 0.5 clock cycle. We can design an XOR gate further in order to optimize these parameters like the number of cells (Package density), area and delay (Speed). Modification in the Boolean expression of the XOR gate in an innovative way or a different methodology of placement of cells can be used to achieve the best result. In the multiplexer circuit as per the latest achievement in 2:1 mux and 4:1 mux, a saving of 63.15% number of QCA cells and 66% of the area as compared to previous design approaches is achieved. The same holds as the thumb rule for implementing any digital circuitry in QCA. Researchers can make further optimization in such digital circuits for digitalization and revolution in the field of QCA.
The generation of a novel clocking scheme is needed. Power and thermal analysis is also one of the major areas to be considered for improvement and optimization. New tools can be designed to optimize quantum devices. New software for quantum dot cellular automata will be a future work that can combine parameter estimation like power, thermal analysis, and number of cells, delay and total area of the circuit layout. This will help the researchers to get the details of the circuit all at one place. Further, this will make data analysis available to the fabrication industry in an easy and faster way. QCA has applications in almost every field with miniaturization to make global digitalization. One such novel NOT gate with analysis is indicated. Standard NOT gate with fork shape has 9 cells, polarization of 9.51 with an area of 7198 nm 2. Thus, the novel gate provides an improvement of 55% in the number of cells, polarization raised by 0.33 and 80.77% improvement in total area.