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Research Article |

Leakage Current Analysis of FinFET Based 7T SRAM at 32nm Technology

Author(s): Dr. Chhavi Saxena

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 3, issue 2

Publisher : FOREX Publication

Published : 30 june 2015

e-ISSN : 2347-470X

Page(s) : 31-34

DOI: https://doi.org/10.37391/IJEER.030206

Abstract

FinFETs can be a replacement for bulk- CMOS transistors in many different designs. Its low leakage/standby power property makes FinFETs a desirable option for memory sub-systems. Memory modules are widely used in most digital and computer systems. Leakage power is very important in memory cells since most memory applications access only one or very few memory rows at a given time. As technology scales down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the32nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs efficiency, called variable-supply voltage schemes. In this paper, we’ve illustrated the design and implementation of FinFET based 4x4 SRAM cell array by means of one bit 7T SRAM. FinFET based 7T SRAM has been designed and analysis have been carried out for leakage current, dynamic power and delay. For the validation of our design approach, output of FinFET SRAM array have been compared with standard CMOS SRAM and significant improvements are obtained in proposed model.

Keywords: FinFET, 7T SRAM Cell, leakage current, Delay.




Dr. Chhavi Saxena*, Associate Professor, Department of ECE, Maharana Pratap College of Technology, Gwalior, Madhya Pradesh, India; Email: vlsi.chhavi@gmail.com

    [1] D. M. Fried, “The Design Fabrication and Characterization of Independent-Gate FinFETs”, Cornell University, 2004.
    [2] S. R. Patel, K. R. Bhatt, and R. Jani, “Leakage current reduction techniques in SRAM,” International Journal of Engineering Research & Technology, vol. 2, no. 1, 2013.
    [3] U. Chaudhari and R. Jani, “A Study of circuit level leakage reduction techniques in cache memories, “International Journal of Engineering Research and Applications, vol. 3, no. 2, pp. 457–460, 2013.
    [4] Raj B. et al., “Nanoscale FinFET based SRAM cell Design: Analysis of performance Metric, process variation, underlapped FinFET and temperature effect”, IEEE circuits and systems magazine, vol.11, issue2, pp.38-50, August 2011.
    [5] Soleimani S. et al, “temperature dependence of propagation delay characteristics in FinFET circuits”, IEEE International conference on microelectronics, pp. 276-279, Dec. 2008.
    [6] Kazuhiko E. et al, “Independent double-gate FinFET SRAM for leakage current reduction”, IEEE electron device letters, vol.30,no.7, pp. 757-759, July 2009.
    [7] D. C. Gupta and A. Raman, “Analysis of leakage current reduction techniques in SRAM cell in 90 nm CMOS technology,” International Journal of Computer Applications, vol. 50, no. 19, 2012.
    [8] B. Raj, A. K. Saxena, and S. Das gupta, “Nanoscale FinFET based SRAM cell design: analysis of performance metric, process variation, underlapped FinFET, and temperature effect,” IEEE Circuits and Systems Magazine, vol. 11, no. 3, pp. 38–50, 2011.
    [9] Zhang L. Et al, “Leakage power reduction techniques of 55nm SRAM cells”, IETE technical Review, vol. 28, Issue 2, pp. 315-31, Apr 2011.

Dr. Chhavi Saxena (2015), Leakage Current Analysis of FinFET Based 7T SRAM at 32nm Technology. IJEER 3(2), 31-34. DOI: 10.37391/IJEER.030206.