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Research Article |

On-Chip AMBA Bus Based Efficient Bridge between High Performance and Low Peripheral Devices

Author(s): Anurag Shrivastava*, Arjun J Anil, Rahul Nair and Dr. Sudhir Kumar Sharma

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 4, Issue 1

Publisher : FOREX Publication

Published : 30 march 2016

e-ISSN : 2347-470X

Page(s) : 5-9

DOI: https://doi.org/10.37391/IJEER.040102

Abstract

Today’s scenario of SOC deals with integrity and sharing of information or data with various level of communication. AMBA bus protocol has been proposed by ARM community to justify the uneven demand of integrity .In this paper functional description and implementation of high peripheral devices supporting protocol AXI2.0 and its interface between low peripheral devices has been proposed. The connection named as bridge take care of the protocol mismatch and operates on data transfer for uneven speed demand. Asynchronous FIFO has been considered to avoid the complex handshaking mechanism. The design has been implemented within VHDL and implemented on Xilinx Virtex 4.

Keywords: AMBA bus protocol, AXI2.0, Asynchronous FIFO, VHDL, Xilinx Virtex 4.




Anurag Shrivastava*, Research Scholar Department of ECE, JNU Jaipur; Email: shrivastavaanurag@rediffmail.com

Dr. Sudhir Kumar Sharma, Professor Department of ECE, JNU Jaipur; Email: sudhir.732000@gmail.com

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Anurag Shrivastava and Dr. Sudhir Kumar Sharma (2016), On-Chip AMBA Bus Based Efficient Bridge between High Performance and Low Peripheral Devices. IJEER 4(1), 5-9. DOI: 10.37391/IJEER.040102.