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Research Article |

Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture

Author(s): S. Munaf*, Dr. A. Bharathi and Dr. A. N. Jayanthi

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 4, Issue 1

Publisher : FOREX Publication

Published : 30 march 2016

e-ISSN : 2347-470X

Page(s) : 10-15

DOI: https://doi.org/10.37391/IJEER.040103

Abstract

Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumping the data bus and an I/O buffer between the memory and the data bus of DDR SDRAM. All modules have been designed at behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.

Keywords: Coarse- grained reconfigurable architecture, configuration cache, embedded system, loop pipelining, low power.




S. Munaf*, Assistant Professor Department of ECE, Sri Ramakrishna Institute of Technology, Coimbatore- 641042, India; Email: shrivastavaanurag@rediffmail.com

Dr. A. Bharathi , Professor Department of IT, Bannari Amman Institute of Technology, Sathyamangalam-638401, India; Email: shrivastavaanurag@rediffmail.com

Dr. A. N. Jayanthi, Associate Professor Department of ECE, Sri Ramakrishna Institute of Technology, Coimbatore- 641042, India; Email: sudhir.732000@gmail.com

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S. Munaf, Dr. A. Bharathi and Dr. A. N. Jayanthi (2016), Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture. IJEER 4(1), 10-15. DOI: 10.37391/IJEER.040103.