Research Article |
Effect of changes in supply voltage on power consumption of digital CMOS delay lines
Author(s): Pankaj Prajapati* and Dr. Shyam Akashe
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 4, issue 4
Publisher : FOREX Publication
Published : 30 December 2016
e-ISSN : 2347-470X
Page(s) : 118-121
Abstract
In the beginning of the last decade, battery-powered hand-held devices such as mobile phones and laptop computers emerged. For that application we have to design a device which will consume minimum amount of energy. For that reason in this article we focused on power consumption and how to calculate the power. In this paper, an analysis of different delay lines based on CMOS architecture has been done. The effect of supply voltage on digital delay lines has been analysed as how supply voltage affected the value of power consumption of the digital delay line. After the analysis of those performance parameters, the trade-off has been made for better performance of delay lines.
Keywords: Power consumption
, delay line
, CMOS
, supply voltage
.
Pankaj Prajapati*, PG Scholar Department of Electronics and communication ITM University, Gwalior ; Email: er.pankaj.prajapatii@gmail.com
Dr. Shyam Akashe, Professor Electronics and communication Department ITM University, Gwalior; Email: shyam.akashe@itmuniversity.ac.in
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[1] Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic “Digital Integrated Circuits—A Design Perspective (2nd Ed), 2002”.
-
[2] Sung-Mo Kang, Yusuf Leblebigi “CMOS digital integrated circuits Analysis and Design” (second edition), 2003.
-
[3] Neil H. E. Weste, David Money Harris “CMOS VLSI Design A Circuits and Systems Perspective” Fourth Edition, 2011.
-
[4] V. Ramakrishnan, Poras T. Balsara “A Wide-Range, High- Resolution, Compact, CMOS Time to Digital Converter” Center for Integrated Circuits and Systems the University of Texas at Dallas, Richardson, TX 75083 in 2006.
-
[5] Shahrzad Naraghi “Time based analog to digital converter” in 2009.
-
[6] Manobu TANAKA, Hirokazu IKEDA, Mitsuo IKEDA, and Susumu INABA “Development of Monolithic Time-to-Amplitude Converter for High Precision TOF Measurement” National Laboratory for High Energy Physic3 1-1 Oho, 905 Japan, April 1991.
-
[7] V. Ramakrishnan, Poras T. Balsara “A Wide-Range, High- Resolution, Compact, CMOS Time to Digital Converter” Center for Integrated Circuits and Systems The University of Texas at Dallas, Richardson, TX 75083 in 2006 ramav@student.utdallas.edu, poras@utdallas.edu.
-
[8] Yasuo Arai, Member, IEEE, and Masahiro Ikeno “A time digitiser CMOS gate array with a 250ps time resolution” in feb. 1996.
-
[9] Gordon W. Roberts, Fellow, IEEE, and Mohammad Ali- Bakhshian “A Brief Introduction to Time to-Digital and Digital-to- Time Converters” in 2010.
-
[10] Jim stiles “Power delay product”, The University of Kansas 11- 5-2004.
-
[11] Chin Hwee Tan,“Optimisation of power and delay in VLSI circuits using transistor Sizing and input ordering “University of Illinois at urbana chmpaign, 1992.
-
[12] Antti Mantyniemi “An integrating CMOS high precision time to digital converter based on stabilised three stage delay line interpolation” OULU 2004.
-
[13] A. Aloisio. P. Branchini, R. Cicalese, R. Giordano, V. Izzo, S. Loffredo, R. Lomoro “High-Resolution Time to Digital Converter in Field Programmable Gate Array, 2008.
-
[14] Delay line, Rombus industries Inc. 1998.
-
[15] G. S. Jovanovi’ c, M. K. Stoj cev “Vernier’s Delay Line Time to Digital Converter, Scientific publications of the state university of novi pazar, Vol. 1, PP11-20, 2009.
-
[16] Julius Smith and Nelson Lee “Computational acoustic modelling with digital delay” centre for computer research in music and acoustic (CCRMA) department of music, Stanford University, California 2008.
-
[17] www.interfacebus.com “Dictionary of Electronics”.
-
[18] Hezler, S “Time to Digital Converters” in Springer 2010.
-
[19] www.birmingham.ac.uk “Emerging Device Technology > Delay line filters.