I. J. of Electrical & Electronics Research
Research Article | 
Effect of changes in supply voltage on power consumption of digital CMOS delay lines
Author(s): Pankaj Prajapati* and Dr. Shyam Akashe
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 4, issue 4
Publisher : FOREX Publication
Published : 30 December 2016
e-ISSN : 2347-470X
Page(s) : 118-121
Abstract
In the beginning of the last decade, battery-powered hand-held devices such as mobile phones and laptop computers emerged. For that application we have to design a device which will consume minimum amount of energy. For that reason in this article we focused on power consumption and how to calculate the power. In this paper, an analysis of different delay lines based on CMOS architecture has been done. The effect of supply voltage on digital delay lines has been analysed as how supply voltage affected the value of power consumption of the digital delay line. After the analysis of those performance parameters, the trade-off has been made for better performance of delay lines.
Keywords: Power consumption, delay line, CMOS, supply voltage.
Pankaj Prajapati*, PG Scholar Department of Electronics and communication ITM University, Gwalior ; Email: er.pankaj.prajapatii@gmail.com
Dr. Shyam Akashe, Professor Electronics and communication Department ITM University, Gwalior; Email: shyam.akashe@itmuniversity.ac.in
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