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Effect of changes in supply voltage on power consumption of digital CMOS delay lines

Author(s): Pankaj Prajapati* and Dr. Shyam Akashe

Publisher : FOREX Publication

Published : 30 December 2016

e-ISSN : 2347-470X

Page(s) : 118-121




Pankaj Prajapati*, PG Scholar Department of Electronics and communication ITM University, Gwalior ; Email: er.pankaj.prajapatii@gmail.com

Dr. Shyam Akashe, Professor Electronics and communication Department ITM University, Gwalior; Email: shyam.akashe@itmuniversity.ac.in

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Pankaj Prajapati and Dr. Shyam Akashe (2016), Effect of changes in supply voltage on power consumption of digital CMOS delay lines. IJEER 4(4), 118-121. DOI: 10.37391/IJEER.040402.