FOREX Press I. J. of Electrical & Electronics Research
Support Open Access
  • Home/
  • IJEER-070301

Research Article |

Design of Microstrip Patch Antenna with DGS for GSM application

Author(s): Srashti Sharma1 and Vandana Vikas Thakare2

Published In : International Journal of Electrical and Electronics Research (IJEER)        volume 7, issue 3

Publisher : FOREX Publication

Published : 31 july 2019

e-ISSN : 2347-470X

Page(s) : 11-18

DOI: https://doi.org/10.37391/IJEER.070301

Abstract

As technology scales towards nanometer regime the leakage power consumption emerging as a major design constraint for the analysis and design of complex arithmetic logic circuits. In this paper, comparative analysis of standby leakage current and sleep to active mode transition leakage current has been done. An innovative power gating approaches is also analyzed which targets maximum reduction of major leakage current. To analyze we introduce the stacking power gating scheme, we implemented this scheme on carry look ahead adder circuit and then simulation has been done using stacking power gating scheme with 45nm technology parameters. The simulation results by using this scheme in BPTM 45nm technology with supply voltage of 0.9V at room temperature shows that leakage reduction can be improved by 47.14% as on comparison with single transistor gating scheme on comparing with conventional schem Also, another novel approach has been analyzed with diode based stacking power gating scheme for further reduction in leakage power. The simulation results depicts that the analyzed design leads to efficient carry look ahead adder circuit in terms of leakage power, active power and delay.

Keywords: High Performance Power Gating Schemes, Leakage power, sleep to active mode transition.




Yogesh Kulshethra*, M.E student GICTS, Gwalior, INDIA; Email: vlsi.chhavi@gmail.com

Manish Kule , Assistant Professor, GICTS, Gwalior, INDIA

    [1] Radu Zlatanovici, Sean Kao, Borivoje Nikolic, “Energy-Delay Optimization of 64-Bit Carry-Look ahead Adders With a 240ps 90nm CMOS Design Example,” IEEE J. Solid State circuits, Vol. 44 ,No.2,February 2012.
    [2] K. Navi, O. Kavehei, M. Rouholamini, A. Sahafi, S .Mehrabi, N. Dadkhai, “Low-Power and High-Performance 1-bit CMOS Full Adder Cell,” Journal of Computers, Academy Press, Vol.3, No.2, February 2015.
    [3] Rabaey J. M., A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, A Design Perspective, 2nd Prentice Hall, Englewood Cliffs, NJ, 2002.
    [4] Pren R. Zimmermann, W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE J. Solid- State Circuits, Vol. 32, pp. 1079– 1090, July 2011.
    [5] “International Technology Roadmap for Semiconductors,” Semiconductor Industry Association, 2005. [Online]. Available: http://public.itrs.net.
    [6] Shilpi Birla, Neeraj K. Shukla, Manisha Pattanaik and R.K Singh “Analysis of the data stability and leakage reduction in the various SRAM cells topologies”, International Journal of engineering science & technology computer (IJEST), Singapore, vol. 2(7), 2010, pp. 2936-2944, ISSN: 0975- 5462.
    [7] M. Tie, H. Dong, T. Wong, Xu Cheng, “ Dual- Vth leakage reduction with fast clock skew scheduling enhancement”, IEEE conference on Design Automation & Test in Europe, 2016, pp. 520-525.
    [8] R. Bhanuprakash, Manisha Pattanaik, S.S Rajput and Kaushik Mazumdar, “ Analysis & reduction of ground bounce noise and leakage current during mode transition of stacking power gating logic circuits” , proceedings of IEEE TENCON Singapore, pp. 1-6, 2014.
    [9] Shilpi Birla, Neeraj Kr. Shukla, R.K Singh and Manisha Pattanaik, “ Device and circuit design challenges for low leakage SRAM for ultra-low power applications”, Canadian Journal of Electrical and Electronics Engineering ( EEE) Canada, USA, vol.1, no.7, Dec. 2016, pp. 156-157, ISSN:1923-0540.
    [10] M.H. Chowdhary, G. Gjanc, J.P. Khaled, “Controlling ground bounce noise in power gating scheme for system- on- chip,” in Proc. Int. Symposium on VLSI (2016), pp. 437-440.
    [11] Rahul Singh, Ah Reum Kim, Kim So Young, Kim Suhan, “ A three- step power gating turn-on technique for controlling ground bounce noise,” in Proc. Int. Symposium on Low power electronics and design,” ( 2016), pp. 171-176.
    [12] Ikeda, Teii, Kungen, “Origin of reverse leakage current in n- type crystalline diamond/ p type silicon heterojunction diodes”, IEEE Applied Science Physics Letter, vol. 94 (7) (2015).
    [13] Y. Lie, C. Hong Hwang, C. Le Chen and S. Chung Lou, “UV illumination technique for leakage current reduction in a Si: H thin film transistors”, IEEE transactions on Electron devices, vol. 55 (11) (2016) pp. 3314-3318.
    [14] Subramanian, A.R Singhal, R. Chi- Chao Wang Yu Cao, “Design rule optimization of regular layout for leakage reduction in nanoscale design” IEEE conference on Design Automation , ASPDAC , 2008, pp. 474- 479.
    [15] D. Dwevedi, K. Sunil Kumar, “Power rail noise minimization during mode transition in a dual core processor,” IEEE conference on advances in computing control and Telecommunication technology (2016), pp. 135-139.

Yogesh Kulshethra and Manish Kule (2019), Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes. IJEER 7(3), 11-18. DOI: 10.37391/IJEER.070301.