I. J. of Electrical & Electronics Research
Research Article | 
FPGA Design of Real Time Hardware for Face Detection
Author(s) : Kibum Suh
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 10, Issue 2
Publisher : FOREX Publication
Published : 10 June 2022
e-ISSN : 2347-470X
Page(s) : 202-206
Abstract
This paper proposes the hardware architecture of face detection FPGA hardware system using the AdaBoost algorithm. The proposed structure of face detection hardware system is possible to work in 30 frames per second and in real time. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data by MATLAB, and finally detected the face using this data. This paper describes the face detection hardware structure composed of image scaler, integral image extraction, face comparing, memory interface, data grouper and detected result display. The proposed circuit is so designed to process one point in one cycle that the proposed design can process full HD (1920x1080) image at 70MHz, which is approximate 2316087 x 30 cycle.
Keywords: FPGA, Adaboost, Real time, face detection
Kibum Suh, Department of Rail System, Woosong University, Deajeon, South Korea; Email: kbsuh@wsu.ac.kr
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Kibum suh (2022), FPGA Design of Real Time Hardware for Face Detection. IJEER 10(2), 202-206. DOI: 10.37391/IJEER.100226.