FOREX Press I. J. of Electrical & Electronics Research
Support Open Access
  • Home/
  • IJEER-100336

Research Article |

An Optimized Pipeline Based Blind Source Separation Architecture for FPGA Applications

Author(s): M. R. Ezilarasan1 and J. Britto Pari2

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 10, Issue 3

Publisher : FOREX Publication

Published : 18 September 2022

e-ISSN : 2347-470X

Page(s) : 632-638

DOI: https://doi.org/10.37391/IJEER.100336

Abstract

This work proposes an optimized blind source separation (BSS) architecture utilizing accumulator-based radix 4 multipliers incorporating an independent component analysis (ICA) approach. The signal observed in distinct environmental conditions degraded from its original form. ICA-based filtering is a suitable choice for recovering the desired signal components. Field Programmable Gate Array (FPGA) implementation makes the design much more attractive in high-performance. The proposed BSS-ICA architecture consists of three Random Access Memory (RAM) units and a pipeline-based accumulator radix-4 multiplier. In this work, different source signals such as sinusoidal and speech signals are considered for the analysis. The sources signals are combined with the mixing signal and the resultant signals are processed using the proposed architecture. The pipeline utilized accumulator radix-4 multiplier structure in the proposed design provides good performance in terms of speed and area. The performance of the proposed architecture is analysed using Simulink and FPGA and the results are reported. The speed of the proposed structure is improved by about 19.33% when compared with the conventional design. Likewise, the area (slices) optimization of about 27.27% is achieved for the proposed structure when examined with the existing approach. Hence, the proposed architecture separates the designed signal component with a lesser area and high speed.

Keywords: BSS, FPGA, ICA, Radix-4 Booth Algorithm




M. R. Ezilarasan, Assistant Professor. Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R & D Institute of Science and Technology, Avadi, Chennai, TN, India; Email: arasanezil@gmail.com

J. Britto Pari, Associate Professor, Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R & D Institute of Science and Technology, Avadi, Chennai, TN, India; Email: brittopari@yahoo.co.in

    [1] Vinita Singh.,” FPGA Implementation of Blind Source Separation using a novel ICA Algorithm” IEEE International conference on consumer Electronics., 2017[Cross Ref]
    [2] P. Berg and M. Scherg, “A multiple source approach to the correction of eye artifacts,” Electroencephalogr. Clin. Neurophysiol., vol. 90, pp. 229–241, 1994.[Cross Ref]
    [3] R. Vigario, “Extraction of ocular artifacts from EEG using independent component analysis,” Electroencephalogr. Clin. Neurophysiol., vol. 103, pp. 395–404, 1997.[Cross Ref]
    [4] T. W. Lee, Independent Component Analysis: Theory and Applications. Boston, MA: Kluwer, 1998.[Cross Ref]
    [5] A. Hyvärinen and E. Oja, “Independent component analysis: Algorithms and applications,” Neural Network., vol. 13, pp. 411–430, May 2000.[Cross Ref]
    [6] A. Nordin, C. Hsu, and H. Szu, “Design of FPGA ICA for hyperspectral imaging processing,” in Proc. SPIE Signal Image Process., Mar. 2001, vol. 4391, pp. 444–454.[Cross Ref]
    [7] H. Du and H. Qi, “An FPGA implementation of parallel ICA for dimensionality reduction in hyperspectral images,” in Proc. IEEE, 2004, pp:3257-3260.[Cross Ref]
    [8] C. M. Kim, H. M. Park, T. Kim, Y. K. Choi, and S. Y. Lee, “FPGA implementation of ICA algorithm for blind signal separation and adaptive noise canceling,” IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1038–1046, Sep. 2003.[Cross Ref]
    [9] A. R. Omondi and J. C. Rajapakse, “Neural networks in FPGAs,” in Proc. Int. Conf. Neural Inf. Process., Nov. 2002, vol. 2, pp. 954–959.[Cross Ref]
    [10] L.Neo Oliva moreno “Implementation of Infomax ICA Algorithm for blind source separation” Electronics, Robotics and Automotive mechanics conference, 2008[Cross Ref]
    [11] Hyvarinen., “independent component analysis: Recent advances” Phil. transaction 2013[Cross Ref]
    [12] Hyvarinen., J Karhunen “Independent component analysis” vol 46,John Wiley & Sons,2004[Cross Ref]
    [13] S. Mirzaei,Y. Norouzi, andH.Van Hamme, “Two-stage blind audio source counting and separation of stereo instantaneous mixtures using Bayesian tensor factorisation,” IET Signal Process., vol. 9, no. 8, pp. 587–595, 2015. [Cross Ref]
    [14] B. Laufer-Goldshtein, R. Talmon, and S. Gannot, “Source counting and separation based on simplex analysis,” IEEE Trans. Signal Process.,vol. 66, no. 24, pp. 6458–6473, Dec. 2018.[Cross Ref]
    [15] S. Araki, T. Nakatani, H. Sawada, and S. Makino, “Blind sparse source separation for unknown number of sources using Gaussian mixture model fitting with dirichlet prior,” in . IEEE, 2009, pp. 33–36.[Cross Ref]
    [16] B. Murali Krishna, Chella Santhosh, S.K. Khasimbee (2022), FPGA Implementation of High-Performance s-box Model and Bit-level Masking for AES Cryptosystem. IJEER 10(2), 171-176. DOI: 10.37391/IJEER.100221.[Cross Ref]
    [17] Kibum suh (2022), FPGA Design of Real Time Hardware for Face Detection. IJEER 10(2), 202-206. DOI: 10.37391/IJEER.100226.[Cross Ref]
    [18] Guard Kanda and Kwanki Ryoo (2022), Design of an Integrated Cryptographic SoC Architecture for Resource-Constrained Devices. IJEER 10(2), 230-244. DOI: 10.37391/IJEER.100231.[Cross Ref]

M. R. Ezilarasan and J. Britto Pari, A. Dahir Alramadan and M. AL-Shakban (2022), An Optimized Pipeline Based Blind Source Separation Architecture for FPGA Applications. IJEER 10(3), 632-638. DOI: 10.37391/IJEER.100336.