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Research Article |

Deep Neural Learning based Deming Regression Adder Enhancement on Digital Multiplier for 3D Graphical Applications in VLSI Circuits

Author(s): M. Renuka1 and G. Mary Valantina2

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 11, Issue 2

Publisher : FOREX Publication

Published : 30 April 2023

e-ISSN : 2347-470X

Page(s) : 242-252

DOI: https://doi.org/10.37391/IJEER.110202

Abstract

This work aims to investigate 3D Technology to provide better performance enhancement for several generations. The three-dimensional integrated circuit allows better integration density, faster on-chip communications, and heterogeneous integration. The goal of this research is to reduce time consumption and power consumption by introducing the Deep Neural Learnt Deming Regression Based Ladner-Fisher Adder Enhancement (DNLDR-LFAE) Technique in VLSI circuits. Input information (carry inputs) is taken for input layer and transmits to hidden layer 1. Deeming regression analysis has performed at hidden layer 1 to pre-process input data and it is send to hidden layer 2. In that layer, performs carry generation as well as post-processing as well as output outcomes have enclosed with convolution. Finally, at output layer, outcomes were attained to execute well-organized adder improvement of digital multiplier by lesser power as well as time consumption. DNLDR-LFAE Technique measured in terms of power, location and time consumption. An outcome of DNLDR-LFAE Technique decreases time and power consumption of adder enhancement than other methods. The hardware complexity of proposed technique obtains minimized by upto 52% to 63% when designed by Ladner-Fisher Adder.

Keywords: Very Large Scale Integration, Integrated Circuit, Ladner-Fischer, Adder Enhancement, Carry Generation.




M. Renuka*, Research Scholar, Department of ETCE, Sathyabama Institute of Science and Technology, Chennai, India; Email: mannrenu1@gmail.com

G. Mary Valantina, Associate Professor, Department of CSE, Saveetha school of engineering , Chennai, India

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M. Renuka and G. Mary Valantina (2023), Deep Neural Learning based Deming Regression Adder Enhancement on Digital Multiplier for 3D Graphical Applications in VLSI Circuits. IJEER 11(2), 242-252. DOI: 10.37391/IJEER.110202.