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Designing of Tunnel FET and FinFET using Sentaurus TCAD and Finding their Characteristics

Author(s): Debashish Dash*, Shaik Abdul Rahiman, C. Pavitra Chowdary and Sagar Deo Singh

Publisher : FOREX Publication

Published : 20 September 2023

e-ISSN : 2347-470X

Page(s) : 754-759




Debashish Dash*, Assistant Professor, School of Electronics (SENSE), Vellore Institute of Technology, Vellore, India; Email: debashish.dash@vit.ac.in

Shaik Abdul Rahiman, Student, School of Electronics (SENSE), Vellore Institute of Technology, Vellore, India; Email: shaikabdul.rahiman2022@vitstudent.ac.in

C. Pavitra Chowdary, Student, School of Electronics (SENSE), Vellore Institute of Technology, Vellore, India; Email: pavithrachowdary.c2022@vitstudent.ac.in

Sagar Deo Singh, Student, School of Electronics (SENSE), Vellore Institute of Technology, Vellore, India; Email: sagardeosingh99@gmail.com

    [1] Karthik, K.R.N., Pandey, C.K., 2023, A Review of Tunnel Field-Effect Transistors for Improved ON-State Behaviour. Silicon 15, 1–23.
    [2] Kujur, K.S., Rasheed, G. & Sridevi, S., 2022, InGaAs-Si Double Pocket-Dual Gate Tunnel FET Based 7T SRAM Design. Silicon 14, pp. 10087–10099.
    [3] Singh A, Pandey CK, Nanda U., 2022, Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction. Microelectronics Journal, 126:105512.
    [4] Pandey C. K., Dash D. & Chaudhury S., 2020, Improvement in analog/RF performances of SOI TFET using dielectric pocket, International Journal of Electronics, 107:11, 1844-1860.
    [5] Amrouch H., Santen Victor M. van, Pahwa Girish, Chauhan Yogesh, Jorg Henkel Jorg. 2020. 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 637-644.
    [6] Pandey C. K., Dash D. & Chaudhury S., 2019, Approach to suppress conduction in Tunnel FET using dielectric pocket, Micro & Nano Letters, 14:1, pp. 86-90.
    [7] Goswami, R. and Bhowmick, B., 2019. Comparative analyses of circular gate TFET and heterojunction TFET for dielectric-modulated label-free biosensing. IEEE Sensors Journal, 19:21, pp.9600-9609.
    [8] Pal, R.S., Sharma, S. and Dasgupta, S., 2017, March. Recent trend of FinFET devices and its challenges: A review, in 2017 Conference on Emerging Devices and Smart Systems (ICEDSS), pp. 150-154.
    [9] Das, R., Goswami, R. and Baishya, S., 2016. Tri-gate heterojunction SOI Ge-FinFETs. Superlattices and Microstructures, 91, pp.51-61.
    [10] Goswami, R. and Bhowmick, B., 2016. An analytical model of drain current in a nanoscale circular gate TFET. IEEE Transactions on Electron Devices, 64(1), pp.45-51.
    [11] Jurczak, M., Collaert, N., Veloso, A., Hoffmann, T. and Biesemans, S., 2009, October. Review of FINFET technology, in 2009 IEEE international SOI conference, pp. 1-4.
    [12] Ajaykumar Dharmireddy and Sreenivasarao Ijjada (2023), Performance Analysis of Variable Threshold Voltage (ΔVth) Model of Junction less FinTFET. IJEER 11(2), 323-327. DOI: 10.37391/IJEER.110211.

Debashish Dash, Shaik Abdul Rahiman, C. Pavitra Chowdary and Sagar Deo Singh (2023), Designing of Tunnel FET and FinFET using Sentaurus TCAD and Finding their Characteristics. IJEER 11(3), 754-759. DOI: 10.37391/ijeer.110318.