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Research Article |

Hybrid Data Driven Clock Gating and Data Gating Technique for Better Saving Power in ALU RISC-V

Author(s): Minh Huan Vo

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 12, Issue 1

Publisher : FOREX Publication

Published : 20 march 2024

e-ISSN : 2347-470X

Page(s) : 238-246

DOI: https://doi.org/10.37391/IJEER.120133

Abstract

The study proposes a hybrid data driven clock gating and data gating technique which is applied to ALU in RISC-V. By doing so, the proposed low power technique can improve the power saving efficiency. The proposed low power technique is compared with various low power techniques such as latch-free based clock gating, latch-based clock gating, single data driven clock gating, and single data gating. The results show that the proposed low power ALU saves 46.67% power consumption compared to original ALU. The proposed ALU also shows better saving power than the latch-free based clock gating, latch-based clock gating, sdata driven clock gating, and data gating from 10.84% to 22.23%. The comparison is also implemented on CPU which consists of memory, ALU and control unit. The proposed low power CPU saves 12.11% at least compared to the original CPU. However, the proposed low power CPU is reduced to 15.1% maximum frequency operation compared to the original CPU. The area overhead of the proposed ALU also increased to 33 LUTS (8.2%) and 2 registers (1.6%) compared to the original ALU.

Keywords: ALU, Clock gating, Data driven clock gating, Data gating, RISC-V, Low power technique.




Minh Huan Vo*, Ho Chi Minh University of Technology and Education; Email: huanvm@hcmute.edu.vn

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Minh Huan Vo (2024), Hybrid Data Driven Clock Gating and Data Gating Technique for Better Saving Power in ALU RISC-V. IJEER 12(1), 238-246. DOI: 10.37391/IJEER.120133.