f Creating a Logic Divider Based on BCD and Utilizing the Vedic Direct Flag Method
FOREX Press I. J. of Electrical & Electronics Research
Support Open Access

Research Article |

Creating a Logic Divider Based on BCD and Utilizing the Vedic Direct Flag Method

Author(s): Perumal B, Balamanikandan A*, Arunraja A, Venkatachalam K, Shaik Rahamtula and Dhanalakshmi M

Publisher : FOREX Publication

Published : 10 August 2024

e-ISSN : 2347-470X

Page(s) : 896-904




Perumal B, Electrical and Electronics Engineering, Adhiyamaan college of engineering, Hosur, India; Email: balanperumal.b@gmail.com

Balamanikandan A*, Electronics and Communication Engineering, Mohan Babu University (Erstwhile SreeVidyanikethan Engineering College), Tirupati, India; Email: balamanieee83@gmail.com

Arunraja A, Electronics and Communication Engineering, Christ University, Bangaluru, India; Email: arunraja21@gmail.com

Venkatachalam K, Electronics and Communication Engineering, Audisankara college of engineering and technology, Gudur, India; Email: venkatmek12@gmail.com

Shaik Rahamtula, Electronics and Communication Engineering, Ramireddy Subbarami Reddy (RSR) Engineering College, Kavali, India; Email: dr.rahamath1986@gmail.com

Dhanalakshmi M, Electrical and Electronics Engineering, Selvam College of Technology, Namakkal, India; Email: dhanaeee81@gmail.com

    [1] S Rakshit, S Mondal, A Chakraborty, A Sarkar, D K Kole Synthesis of Reversible Array Divider Circuit, pp701-707, (2019).
    [2] Zahra Ariafar and Mohammad Mosleh, ‘Effective Designs of Reversible Vedic Multiplier’, International Journal of Theoretical Physics (2019) 58:2556–2574.
    [3] RamadeviVemula and K Manjunatha Chari, ‘A review on various divider circuit designs in VLSI’, Conference on Signal Processing and Communication Engineering Systems (SPACES), 2018.
    [4] LamjedTouil and BouraouiOuni, ‘Design of hardware RGB to HMMD converter based on reversible logic’, IET Image Process., 2017, Vol. 11 Iss. 8, pp. 646-655.
    [5] Hafiz Md, HasanBabu, MdSolaiman Mia, Design of a compact reversible fault tolerant division circuit, Microelectronic J (2016), vol. 51, pp. 15-29.
    [6] Ali B and Majid H, ‘Optimized reversible divider circuit’, Int. J. Innovative Computing and Applications, Vol. 7, No. 1, 2016.
    [7] H V Jayashree, SkandaKotethota and V K Agrawal, ‘Reversible circuit design for GCD computation in cryptography algorithms’, Int. J. Circ. Theor. Appl. (2016).
    [8] Siba K P and Arati S, ‘A Novel Vedic Divider Architecture with Reduced Delay for VLSI Applications’, International Journal of Computer Applications, Vol. 120, No.17, pp.0975 – 8887, June 2015.
    [9] Jyotinnayeesubudhi and C Karthick, ‘Implementation of Vedic divider on RSA cryptosystem’, International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS), 2015.
    [10] HuseyinBodur and Resul Kara, ‘Secure SMS Encryption Using RSA Encryption Algorithm on Android Message Application’, 3RD International Symposium on Innovative Technologies in Engineering and Science, June 2015.
    [11] Jayashree H. V, V K Agarwal, P VenkatasreeCharan, and A M ChiragKariappa, ‘Design of Fault Tolerant n Bit Reversible Comparator for optimization of Garbage and Ancilla bits’, Proceedings of International Conference on Circuits, Communication, Control and Computing, 21-22 November 2014.
    [12] Faraz D and Majid H. (2011), ‘A novel nanometric fault tolerant reversible divider’, International Journal of the Physical Sciences Vol. 6, No.24, pp. 5671-5681, 16 October, 2011. doi: 10.5897/IJPS11.981.
    [13] H G Rangaraju, U. Venugopal, K N Muralidhara and K B Raja, ‘Low Power Reversible Parallel Binary Adder/Subtractor’, International Journal of VLSI Design & Communication Systems, 1.3(2010), pp-23-34.
    [14] A. Balamanikandan and K. Krishnamoorthi, “Low area ASIC implementation of LUT–CLA–QTL architecture for cryptography applications,” Wireless Networks, vol. 26, no. 4, pp. 2681–2693, May 2019, doi: 10.1007/s11276-019-02017-3.
    [15] H. Thapliyal and M.B. Srinivas. “Novel Reversible Multiplier Architecture Using Reversible TSG Gate,” in Intern. Conf. on Comp. Syst& App, April 2006.
    [16] R. Landauer, Irreversibility and heat generation in the computational process, IBM J. Res. Dev. 5 (1961) 183–191.
    [17] R. Vemula and K. M. Chari, "A review on various divider circuit designs in VLSI," 2018 Conference on Signal Processing and Communication Engineering Systems (SPACES), 2018, pp. 206-209, doi: 10.1109/SPACES.2018.8316347.
    [18] R. Mishra, "An efficient VLSI architecture for a serial divider," 2017 Devices for Integrated Circuit (DevIC), 2017, pp. 482-486, doi: 10.1109/DEVIC.2017.8073996.
    [19] Ramadevi V, Manjunatha K, Design, and implementation of 64-bit divider using 45 nm CMOS technology Int. J. Pure Appl. Math.20181185293301.
    [20] D. Tomic, J. Mikulic, G. Schatzberger, J. Fellner, A. Baric, Programmable low-frequency divider in 180-nm CMOS technology, in Proceedings of the 43rd International Convention on Information. Communication and Electronic Technology (MIPRO), (2020), pp. 89–92.
    [21] Melchert J Behroozi SLi JKim YSAADI-EC: a quality-configurable approximate divider for energy efficiency IEEE Trans. Very Large Scale Integr. Syst.201927112680269210.1109/TVLSI.2019.2926083.
    [22] Chen LHan JLiu WMontuschi PLombardi F Design, evaluation, and application of approximate high-radix dividersIEEE Trans. Multi Scale Comput. Syst.20184329931210.1109/TMSCS.2018.2817608.

Perumal B, Balamanikandan A, Arunraja A, Venkatachalam K, Shaik Rahamtula, Dhanalakshmi M (2024), Creating a Logic Divider Based on BCD and Utilizing the Vedic Direct Flag Method. IJEER 12(3), 896-904. DOI: 10.37391/IJEER.120321.