f Designing RNS-based FIR filter with optimal area, delay, and power via the use of swift adders and swift multipliers
FOREX Press I. J. of Electrical & Electronics Research
Support Open Access
  • Home/
  • IJEER-120412

Research Article |

Designing RNS-based FIR filter with optimal area, delay, and power via the use of swift adders and swift multipliers

Author(s): Syed AliAsgar* and A Yasmine Begum

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 12, Issue 4

Publisher : FOREX Publication

Published : 30 November 2024

e-ISSN : 2347-470X

Page(s) : 1211-1221

DOI: https://doi.org/10.37391/IJEER.120412

Abstract

Based on the Residue Number System (RNS), Finite Impulse Response filters have gained prominence in digital signal processing due to their efficiency in handling complex computations. This work presents a comprehensive analysis on optimizing area, delay, and power in the FIR filter by exploring different adders and multipliers. Three prominent adders, namely Ripple Carry Adder, Kogge Stone Adder, and Proposed Adder, are evaluated for their impact on area and delay. The choice of adder influences the overall performance of the FIR filter, and a careful selection is made based on the trade-offs between area and delay. Furthermore, various multipliers, including Booth, Baugh-Wooley, Braun, and Array, are compared in terms of their efficiency in power consumption. Multipliers contribute significantly to the overall power consumption, and the analysis involves selecting the most suitable multiplier for achieving the desired power optimization. The various arrangements of swift adders and swift multipliers were suggested and executed in the Finite Impulse Response (FIR) filter and then the RNS algorithm was applied to it. The comparison of 8-tap 8-bit of the proposed adder with the array multiplier shows that the area is reduced by 52.70% with other combinations and by comparing the RCA adder with the array multiplier, the critical path delay is reduced by 38.51% and the maximum frequency is produced by the KSA adder with Braun multiplier which is increased by 29.78% with other combinations.

Keywords: FIR Filter, Residue Number System, Area, Delay, Power, Baugh-Wooley multiplier.




Syed AliAsgar*, Research Scholar, Department of ECE, Mohan Babu University, Tirupati, Andhra Pradesh, India; Email: aliasgarsyed@gmail.com

A Yasmine Begum, Associate Professor, Department of ECE, Mohan Babu University, Tirupati, Andhra Pradesh, India; Email: anwaralyyasmine@gmail.com

    [1] Shaheen Khan, and Zainul Abdin Jaffery, “Modified High-Speed FIR Filter Using DA-RNS Architecture,” International Journal of Advanced Science and Technology, vol. 29, no. 4, pp. 554-570, 2020.B. M, P. N, G. P, S. A. Shaik, S. K. P and S. G. R, "Design of FIR filter with Fast Adders and Fast Multipliers using RNS Algorithm," 2023 4th International Conference for Emerging Technology (INCET), Belgaum, India, 2023, pp. 1-6.
    [2] Balaji. M, Padmaja. N, Gitanjali. P, S. A. Shaik, Siva Kumar. P and Sai Geetesh. R, "Design of FIR filter with Fast Adders and Fast Multipliers using RNS Algorithm," 2023 4th International Conference for Emerging Technology (INCET), Belgaum, India, 2023, pp. 1-6, doi: 10.1109/INCET57972.2023.10170321.
    [3] P. Patronik and S. J. Piestrak, "Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 5, pp. 1031-1039, May 2017.
    [4] Y. Xu, Y. Guo and S. Kimura, "Approximate Multiplier Using Reordered 4–2 Compressor with OR-based Error Compensation," 2019 IEEE 13th International Conference on ASIC (ASICON), Chongqing, China, 2019, pp. 1-4.
    [5] R. Kamal, P. Chandravanshi, N. Jain and Rajkumar, "Efficient VLSI architecture for FIR filter using DA-RNS," 2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE), Hosur, India, 2014, pp. 184-187.
    [6] Rao, E.J., Samundiswary, P. Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application. J Electron Test 37, 623–631 (2021).
    [7] K. Neelima, C. Padma, C. Nalini and M. Balaji, "FIR Filter design using Urdhva Triyagbhyam based on Truncated Wallace and Dadda Multiplier as Basic Multiplication Unit," 2023 IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT), Bhopal, India, 2023, pp. 434-438, doi: 10.1109/ CSNT57126.2023.10134709.
    [8] Garg, B., Patel, S. Reconfigurable Rounding Based Approximate Multiplier for Energy Efficient Multimedia Applications. Wireless Pers Commun 118, 919–931 (2021).
    [9] Seyed Amir Hossein Ejtahed, and Somayeh Timarch, “Efficient Approximate Multiplier Based on a New 1-Gate Approximate Compressor,” Circuits Systems and Signal Processing, vol. 41, pp. 2699-2718, 2022.
    [10] Mostafa Abbasmollaei et al., “A Power Constrained Approximate Multiplier with a High Level of Configurability,” Microprocessors and Microsystems, vol. 90, 2022.
    [11] Shaghayegh Vahdat et al., “LETAM: A Low Energy Truncation-Based Approximate Multiplier,” Computers & Electrical Engineering, vol. 63, pp. 1-17, 2017.
    [12] M. Balaji, N. Padmaja, "Area and Delay Efficient RNS-Based FIR Filter Design Using Fast Adders and Multipliers," SSRG International Journal of Electrical and Electronics Engineering, vol. 10, no. 10, pp. 151-164, 2023.
    [13] G. Reddy Hemantha, S. Varadarajan, and M.N. Giri Prasad, “FPGA Implementation of Speculative Prefix Accumulation-Driven RNS for High-Performance FIR Filter,” Innovations in Electronics and Communication Engineering, pp. 365-375, 2019.
    [14] Burhan Khurshid, and Roohie Naaz Mir, “An Efficient FIR Filter Structure Based on Technology-Optimized Multiply-Adder Unit Targeting LUT-Based FPGAs,” Circuits System and Signal Processing, vol. 36, pp. 600-639, 2017.
    [15] Hamid M. Kamboh, and Shoab A. Khan, “An Algorithmic Transformation for FPGA Implementation of High Throughput Filters,” 2011 7th International Conference on Emerging Technologies, Islamabad, Pakistan, pp. 1-6, 2011.
    [16] Pavel Lyakhov et al., “High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System,” IEEE Access, vol. 8, pp. 209181-209190, 2020.
    [17] Kaplun, D.; Aryashev, S.; Veligosha, A.; Doynikova, E.; Lyakhov, P.; Butusov, D. Improving Calculation Accuracy of Digital Filters Based on Finite Field Algebra. Appl. Sci. 2020, 10, 45. https://doi.org/10.3390/app10010045.
    [18] Che-Wei Tung, and Shih- Hsu Huang, “A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process,” IEEE Access, vol. 8, pp. 87367-87377, 2020.
    [19] Morasa, Balaji, and Padmaja Nimmagadda. 2022. “Low Power Residue Number System Using Lookup Table Decomposition and Finite State Machine Based Post Computation.” Indonesian Journal of Electrical Engineering and Computer Science 6(1): 127–34.
    [20] P. Kishore, R. Sirimalla, K. S. Sushma and R. S. Reddy, "Implementation of Braun and Baugh-Wooley Multipliers Using QCA," 2023 2nd International Conference for Innovation in Technology (INOCON), Bangalore, India, 2023, pp. 1-4.
    [21] M. Saha and A. Dandapat, "Modified Baugh Wooley Multiplier using Low Power Compressors," 2021 2nd International Conference for Emerging Technology (INCET), Belagavi, India, 2021, pp. 1-6.
    [22] M. Balaji, N. Padmaja, A Low Power Transistor Level FIR Filter Implementation using CMOS 45nm Technology, International Journal of Nanotechnology, Vol. 20, No. 1-4, pp. 390-409, 2023.
    [23] K. Yugandhar, V. G. Raja, M. Tejkumar and D. Siva, "High Performance Array Multiplier using Reversible Logic Structure," 2018 International Conference on Current Trends towards Converging Technologies (ICCTCT), Coimbatore, India, 2018, pp. 1-5.
    [24] D. Govekar and A. Amonkar, "Design and implementation of high speed modified booth multiplier using hybrid adder," 2017 International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, 2017, pp. 138-143.
    [25] M. Balaji, and N. Padmaja, “High-Speed DSP Pipelining and Retiming techniques for Distributed-Arithmetic RNS-based FIR Filter Design,” WSEAS Transactions on Systems and Control, vol. 17, pp. 549-556, 2022.
    [26] M. Sarkar, G. S. Taki, Prerna, R. Sengupta and S. N. Ray, "Design of ripple carry adder using CMOS output wired logic based majority gate," 2017 8th Annual Industrial Automation and Electromechanical Engineering Conference (IEMECON), Bangkok, Thailand, 2017, pp. 328-33.
    [27] J. Pathak and S. L. Tripathi, "Novel Obfuscated Secure Architecture for Baugh Wooley Multiplier," 2023 International Conference on Artificial Intelligence and Applications (ICAIA) Alliance Technology Conference (ATCON-1), Bangalore, India, 2023, pp. 1-4.
    [28] Lavanya Maddisetti, Ranjan K. Senapati, and J.V.R. Ravindra, Image Multiplication with a Power-Efficient Approximate Multiplier Using a 4:2 Compressor, Advances in Image and Data Processing Using VLSI Design, Smart Vision Systems, 13th ed., IOP Publishing Ltd, pp. 13-15, 2021.
    [29] Nikolay N. Kucherov et al., “A High-Speed Residue-to-Binary Converter Based on Approximate Chinese Remainder Theorem,” 2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), Moscow and St. Petersburg, Russia, pp. 325-328, 2018.

Syed AliAsgar and A Yasmine Begum (2024), Designing RNS-based FIR filter with optimal area, delay, and power via the use of swift adders and swift multipliers. IJEER 12(4), 1211-1221. DOI: 10.37391/IJEER.120412.