I. J. of Electrical & Electronics Research
Research Article | 
Design of an Integrated Cryptographic SoC Architecture for Resource-Constrained Devices
Author(s) : Guard Kanda1 and Kwanki Ryoo2
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 10, Issue 2
Publisher : FOREX Publication
Published : 10 June 2022
e-ISSN : 2347-470X
Page(s) : 230-244
Abstract
One of the active research areas in recent years that has seen researchers from numerous related fields converging and sharing ideas and developing feasible solutions is the area of hardware security. The hardware security discipline deals with the protection from vulnerabilities by way of physical devices such as hardware firewalls or hardware security modules rather than installed software programs. These hardware security modules use physical security measures, logical security controls, and strong encryption to protect sensitive data that is in transit, in use, or stored from unauthorized interferences. Without mechanisms to circumvent the ever-evolving attacking strategies on hardware devices and the data that they process or store, billions of dollars will always be lost to attackers who ply their trade by targeting such vulnerable devices. This paper, therefore, proposes an integrated cryptographic SoC architecture solution to this menace. The proposed architecture provides security by way of key exchange, management, and encryption. The proposed architecture is based on a True Random Number generator core that generates secret keys that are used in Elliptic Curve Diffie-Hellman Key Exchange to perform elliptic curve scalar multiplication to obtain public and shared keys after the exchange of the public keys. The proposed architecture further relies on a Key Derivation Function based on the CubeHash algorithm to obtain Derived Keys that provide the needed security using the ChaCha20_Poly1305 Authenticated Encryption with Associated (AEAD) Data Core. The proposed Integrated SoC architecture is interconnected by AMBA AHB-APB on-chip bus and the system is scheduled and controlled using the PicoRV32 opensource RISC-V processor. The proposed architecture is tested and verified on the Virtex-4 FPGA board using a custom-designed GUI desktop application.
Keywords: PicoRV32, ECC, FPGA, TRNG, AEAD_ChaCha20_Poly1305
Guard Kanda, Department of Info, and Comm. Engineering, Hanbat National University, Daejeon, South Korea; Email: guardkanda@gmail.com
Kwangki Ryoo, Department of Info, and Comm. Engineering, Hanbat National University, Daejeon, South Korea; Email: kkryoo@gmail.com
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Guard Kanda and Kwanki Ryoo (2022), Design of an Integrated Cryptographic SoC Architecture for Resource-Constrained Devices. IJEER 10(2), 230-244. DOI: 10.37391/IJEER.100231.