I. J. of Electrical & Electronics Research
Research Article | 
Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso
Author(s) : Sufia Banu1 and Shweta Gupta2
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 10, Issue 2, Special Issue on IEEE-SD
Publisher : FOREX Publication
Published : 30 June 2022
e-ISSN : 2347-470X
Page(s) : 341-346
Abstract
Reduction of Leakage power at nano meter regime has become a challenging factor for VLSI designers. This is owing to the need for low-power, battery-powered portable pads, high-end gadgets and various communication devices. Memories are made up of Static RAM and Dynamic RAM. SRAM has had a tremendous impact on the global VLSI industry and is preferred over DRAM because of its low read and write access time. This research study proposes a new method has been proposed of 6T Static Random Access Memory cell to decrease the leakage current at various technologies. Three source biasing methods are used to minimize the 6T SRAM cell leakage power. The three methods are NMOS diode clamping, PMOS diode clamping and NMOS-PMOS diode clamping at 45 nm and 90 nm technology nodes. This paper also emphasizes on the implementation of 6T SRAM cell using Multiple Threshold CMOS (MTCMOS) technique at 45nm technology. The simulation is achieved and various power dissipations are analyzed at supply voltage of 0.9 V and 0.45 V for 90 nm and 45 nm technology respectively using cadence virtuoso tool. PMOS clamping has shown the reduction in an average power by 82.19% than compared to other two proposed techniques.
Keywords: Clamping diode, Forward body bias, Low Power, MTCMOS, Reverse body bias, Source biasing
Sufia Banu, Research Scholar, Department of ECE, Jain University, Bangalore, India; Email: sufiabanu.ec@gmail.com
Shweta Gupta, Associate Professor, Department of ECE, Jain University, Bangalore, India; Email: shwetagupta832000@gmail.com
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Sufia Banu and Shweta Gupta (2022), Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso. IJEER 10(2), 341-346. DOI: 10.37391/IJEER.100246.