FOREX Press I. J. of Electrical & Electronics Research
Support Open Access

Research Article |

A Classy Memory Management System (CyM2S) using an Isolated Dynamic Two-Level Memory Allocation (ID2LMA) Algorithm for the Real Time Embedded Systems

Author(s) : K. Siva Sundari1, R. Narmadha2 and S. Ramani3

Publisher : FOREX Publication

Published : 30 June 2022

e-ISSN : 2347-470X

Page(s) : 387-393




K. Siva Sundari, Research Scholar, Sathyabama Institute of Science and Technology, Chennai, Tamil Nadu, India; Email: sivasundari2029@gmail.com

R. Narmadha, Professor, Sathyabama Institute of Science and Technology, Chennai, Tamil Nadu, India; Email: narmadha1109@gmail.com

S. Ramani, Associate Professor, Department of Electronics and Communication Engineering, Sreenidhi Institute of Science & Technology, Hyderabad, India; Email: ramanis@sreenidhi.edu.in

[1] Z. Shen, K. Dharsee, and J. Criswell, "Fast Execute-Only Memory for Embedded Systems," in 2020 IEEE Secure Development (SecDev), 2020, pp. 7-14.[Cross Ref]

[2] S.-H. Park, J.-H. Lee, S.-W. Cho, and S.-H. Kim, "A Flash Memory Management Method for Enhancing the Recovery Performance," IEMEK Journal of Embedded Systems and Applications, vol. 13, pp. 235-243, 2018.[Cross Ref]

[3] M. Bazzaz, A. Hoseinghorban, and A. Ejlali, "Fast and predictable non-volatile data memory for real-time embedded systems," IEEE Transactions on Computers, vol. 70, pp. 359-371, 2020.[Cross Ref]

[4] M. Strobel and M. Radetzki, "Design-time memory subsystem optimization for low-power multi-core embedded systems," in 2019 IEEE 13th international symposium on embedded multicore/many-core systems-on-chip (MCSoC), 2019, pp. 347-353.[Cross Ref]

[5] J. Zhou, "Real-time task scheduling and network device security for complex embedded systems based on deep learning networks," Microprocessors and Microsystems, vol. 79, p. 103282, 2020.[Cross Ref]

[6] I. Georgiev and I. Georgiev, "Some Analysis of the Timing Parameters in Real-time Embedded Systems," in 2020 International Conference on Information Technologies (InfoTech), 2020, pp. 1-4.[Cross Ref]

[7] Y.-P. Liang, Y.-T. Fang, S.-H. Chen, Y.-T. Chen, T.-Y. Chen, W.-L. Wang, et al., "Brief Industry Paper: An Energy-Reduction On-Chip Memory Management for Intermittent Systems," in 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2021, pp. 429-432.[Cross Ref]

[8] L. Papadopoulos, C. Marantos, G. Digkas, A. Ampatzoglou, A. Chatzigeorgiou, and D. Soudris, "Interrelations between software quality metrics, performance and energy consumption in embedded applications," in Proceedings of the 21st International Workshop on software and compilers for embedded systems, 2018, pp. 62-65.[Cross Ref]

[9] R. Wittig, M. Hasler, E. Matus, and G. Fettweis, "Queue based memory management unit for heterogeneous MPSoCs," in 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, pp. 1297-1300.[Cross Ref]

[10] V. Venkataramani, M. C. Chan, and T. Mitra, "Scratchpad-memory management for multi-threaded applications on many-core architectures," ACM Transactions on Embedded Computing Systems (TECS), vol. 18, pp. 1-28, 2019.[Cross Ref]

[11] A. A. Clements, N. S. Almakhdhub, S. Bagchi, and M. Payer, "{ACES}: Automatic compartments for embedded systems," in 27th USENIX Security Symposium (USENIX Security 18), 2018, pp. 65-82.[Cross Ref]

[12] T. Poggi, P. Onaindia, M. Azkarate-askatsua, K. Grüttner, M. Fakih, S. Peiró, et al., "A hypervisor architecture for low-power real-time embedded systems," in 2018 21st Euromicro Conference on Digital System Design (DSD), 2018, pp. 252-259.[Cross Ref]

[13] S. Branco, A. G. Ferreira, and J. Cabral, "Machine learning in resource-scarce embedded systems, FPGAs, and end-devices: A survey," Electronics, vol. 8, p. 1289, 2019.[Cross Ref]

[14] M. Labbé and F. Michaud, "Long-term online multi-session graph-based SPLAM with memory management," Autonomous Robots, vol. 42, pp. 1133-1150, 2018.[Cross Ref]

[15] K. Maeng and B. Lucia, "Adaptive dynamic checkpointing for safe efficient intermittent computing," in 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18), 2018, pp. 129-144.[Cross Ref]

[16] R. Tabish, R. Mancuso, S. Wasly, R. Pellizzoni, and M. Caccamo, "A real-time scratchpad-centric OS with predictable inter/intra-core communication for multi-core embedded systems," Real-Time Systems, vol. 55, pp. 850-888, 2019.[Cross Ref]

[17] L. Shaofeng, Q. Lei, and Y. Mengfei, "Verification of a TLSF Algorithm in Embedded System," in Formal Methods and Software Engineering: 22nd International Conference on Formal Engineering Methods, ICFEM 2020, Singapore, Singapore, March 1–3, 2021, Proceedings, 2020, p. 331.[Cross Ref]

[18] S. Weiser, M. Werner, F. Brasser, M. Malenko, S. Mangard, and A.-R. Sadeghi, "TIMBER-V: Tag-Isolated Memory Bringing Fine-grained Enclaves to RISC-V," in NDSS, 2019.[Cross Ref]

[19] R. Zeng, "Embedded Linux Operating System Network Accelerated Operation Method Based on ARM Processor," in 2021 Asia-Pacific Conference on Communications Technology and Computer Science (ACCTCS), 2021, pp. 315-319.[Cross Ref]

[20] X. Ouyang and Y. Zhu, "wfspan: wait-free dynamic memory management," ACM Transactions on Embedded Computing Systems (TECS), 2022.[Cross Ref]

[21] T. Kloda, M. Solieri, R. Mancuso, N. Capodieci, P. Valente, and M. Bertogna, "Deterministic memory hierarchy and virtualization for modern multi-core embedded systems," in 2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2019, pp. 1-14.[Cross Ref]

[22] R. David, J. Duke, A. Jain, V. Janapa Reddi, N. Jeffries, J. Li, et al., "TensorFlow lite micro: Embedded machine learning for tinyml systems," Proceedings of Machine Learning and Systems, vol. 3, pp. 800-811, 2021.[Cross Ref]

[23] A. Rodríguez, J. Valverde, J. Portilla, A. Otero, T. Riesgo, and E. De la Torre, "Fpga-based high-performance embedded systems for adaptive edge computing in cyber-physical systems: The artico3 framework," Sensors, vol. 18, p. 1877, 2018.[Cross Ref]

[24] L. Wang, J. Ye, Y. Zhao, W. Wu, A. Li, S. L. Song, et al., "Superneurons: Dynamic GPU memory management for training deep neural networks," in Proceedings of the 23rd ACM SIGPLAN symposium on principles and practice of parallel programming, 2018, pp. 41-53.[Cross Ref]

[25] S. Munaf, Dr. A. Bharathi, Dr. A. N. Jayanthi (2016), Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture. IJEER 4(1), 10-15. DOI: 10.37391/ijeer.040103. http://ijeer.forexjournal.co.in/archive/volume-4/ijeer-040103.php[Cross Ref]

[26] Victoria Satuluri, Ratna Babu Yellamati (2015), Design of Middleware and Software Embedded Development Kit For Area Based Distributed Mobile Cache System. IJEER 3(3), 44-49. DOI: 10.37391/ijeer.030301. http://ijeer.forexjournal.co.in/archive/volume-3/ijeer-030301.php[Cross Ref]

K. Siva Sundari, R. Narmadha and S. Ramani (2022), A Classy Memory Management System (CyM2S) using an Isolated Dynamic Two-Level Memory Allocation (ID2LMA) Algorithm for the Real Time Embedded Systems. IJEER 10(2), 387-393. DOI: 10.37391/IJEER.100254.