I. J. of Electrical & Electronics Research
Research Article | 
Performance Analysis of Various Fin Patterns of Hybrid Tunnel FET
Author(s): Ajay Kumar Dharmireddy1, Dr Sreenivasa Rao Ijjada2 and Dr I. Hema Latha3
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 10, Issue 4
Publisher : FOREX Publication
Published : 18 October 2022
e-ISSN : 2347-470X
Page(s) : 806-810
Abstract
High speed and low power dissipation devices are expected from future generation technology of Nano-electronic devices. Tunnel field effect transistor (TFET) technology is unique to the prominent devices in low power applications. To minimize leakage currents, the tunnel switching technology of TFETs is superior to conventional MOS FETs. The gate coverage area of different fin shape hybrid tunnel field-effect transistors is more impacted on electric characteristics of drive current, leakage current and subthreshold slope. In this paper design various fin patterns of hybrid TFET devices and shows on better performance as compared with other fin shape hybrid tunnel FET. The TCAD simulation tool is used to determine the characteristics of different fin shape tunnel FET.
Keywords: Tunnel FET, band to band tunneling, fin shape TFET, drive current, leakage current, subthreshold slope
Ajay Kumar Dharmireddy*, Research scholar, Department of Electronics & Communication Engineering, GITAM Deemed to be University, Vishakhapatnam, India; Email: ajaybabuji@gmail.com
Dr Sreenivasa Rao Ijjada, Assistant Professor, Department of Electronics & Communication Engineering, GITAM Deemed to be University, Vishakhapatnam, India; Email: sijjada@gitam.edu
Dr I. Hema Latha, Associate Professor, Department of Electronics & Communication Engineering, Sir C. R. Reddy College of Engineering, Eluru, Andhra Pradesh, India; Email: hemacrr2006@gmail.com
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[1] D.A.kumar, M. S.Babu, S.Rao Ijjada. "SS < 30 mV/dec; Hybrid tunnel FET 3D analytical model for IoT applications", Materials Today: Proceedings, Nov. 2020. [Cross Ref]
-
[2] S. K.valli, T.S.A.Samual, P.Vimala “Performance analysis of triple material tri gate TFET using 3D analytical modelling and TCAD simulation” Int. J. Electron. Comm. (AEÜ), Vol.110, Oct 2019.[Cross Ref]
-
[3] Vimala.P, T. S. A.Samul & M. Karthigai Pandian “Performance Investigation of Gate Engineered tri-Gate SOI TFETs with Different High-K Dielectric Materials for Low Power Applications” Springer Nature B.V., Vol. 24 Sep. 2019. [Cross Ref]
-
[4] A.devi, N., D.A.kumar, I.S.rao.,”Performance Analysis of DGHJ TFET”, IJITE, Vol.9, May 2019, pp.232-234.[Cross Ref]
-
[5] Anjani D.N, D.A.kumar, I.S.Rao “Performance Characteristics of Tfet over Mosfet, DgMosfet and Finfet” TEST engineering &ManagamentMagine, ISSN: 0193 - 4120, Vol.82, Feb. 2020.PP. 6164 – 6170.[Cross Ref]
-
[6] D.A.kumar, I.S.R., P.H.S.T.murthy, “performance analysis of Tri-gate SOI FinFET structure with various fin heights using TCAD simulations”, JARDCS, Vol-11(2) pp-1291-1298, 2019.[Cross Ref]
-
[7] Arun.S T.,Karthigai Pandian,M,.”Comparative Performance Analysis of MGTFET”, Journal of Nano Research ,41, 2016.pp. 1-8[Cross Ref]
-
[8] D.A.Kumar, S.R.Ijjada “A Novel design of SOI based Fin Gate TFET” GCAT, IEEE conference, 1st -3rd Oct 2021.[Cross Ref]
-
[9] M.Schmidt; A. Schäfer; Renato A. M. sawatro; S. Trellenkamp “Line and Point Tunneling in Scaled Si/SiGe Heterostructure TFETs” IEEE Electron Device Letters, Vol.35, issue: 7, July 2014, PP.699 – 701.[Cross Ref]
-
[10] Abhishek Acharya, Abhishek B. Solanki, SudebDasgupta and BulusuAnand “Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective” IEEE Transactions on Electron Devices, VOL. 65, NO. 1, January 2018, PP.322-330.[Cross Ref]
-
[11] Sneh Saurabh, M. Jagadesh Kumar “Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis” Japanese Journal of Applied Physics, Vol.48, June 2009.[Cross Ref]
-
[12] Jang Hyun Kim, Hyun Woo Kim, Garam Kim, Sangwan Kim, and Byung-Gook Park, “Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain” Micromachines Vol.10, 2019.[Cross Ref]
-
[13] Kaishen Ou, Chunxiang Zhu "Germanium Fin Tunnel Field Effect Transistor with Abrupt Tunnel Junction and Large Tunneling Area" IEEE Trans. Electron Devices, vol. 59, no. 2 pp. 292-301, 2018.[Cross Ref]
-
[14] A.K. Dharmireddy, S.R. Ijjada et al., “Rad-Hard Model SOI FinTFET for Spacecraft Application”6th international conference on Micro-electronics, Electromagnetics and Tele communications (ICMEET). 27th, 28th Aug 2021.[Cross Ref]
-
[15] Sufia Banu and Shweta Gupta (2022), Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso. IJEER 10(2), 341-346. DOI: 10.37391/IJEER.100246.[Cross Ref]
-
[16] Pushkar Praveen and Rakesh Kumar Singh (2022), Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies. IJEER 10(2), 381-386. DOI: 10.37391/IJEER.100253.[Cross Ref]
-
[17] Priyanka Saha, Saheli Sarkhel, Subir Kumar Sarkar “3D Modelling and Performance Analysis of Dual Material Tri-Gate Tunnel Field Effect Transistor” IETE Technical review, Volume 36(2), 2019.[Cross Ref]
Ajay Kumar Dharmireddy, Dr Sreenivasa Rao Ijjada and Dr I. Hema Latha (2022), Performance Analysis of Various Fin Patterns of Hybrid Tunnel FET. IJEER 10(4), 806-810. DOI: 10.37391/IJEER.100407.