FOREX Press I. J. of Electrical & Electronics Research
Support Open Access
  • Home/
  • IJEER-100419

Research Article |

Non-Volatile Logic Design Considerations for Energy Efficient Tolerant Variation

Author(s): D. Venkata Prakash1, Anjaiah Talamala2, Mahesh K. Singh3 and Y. Kuntam Yamini Devi4

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 10, Issue 4

Publisher : FOREX Publication

Published : 18 October 2022

e-ISSN : 2347-470X

Page(s) : 868-871

DOI: https://doi.org/10.37391/IJEER.100419

Abstract

Systems design for the non-volatile application must work on less energy or power. The spin-transfer torque-magnetic tunnel junction (STT-MTJ) devices added to the flip-flops which are regarded as non-volatile storage devices. Those are addresses to save the energy of that system stated by the nonvolatile logic. The changes during the production of STT-MTJ and CMOS transistors decrease the yield, which leads to overdesign as well as more energy consumption. The total processes of driver circuitry design for the tradeoffs for backup and restore performance. A new method called the novel method is introduced for flawless energy drivers for given results. The design for the backup time determination and to reduce the energy wastage are mentioned. To get an efficient output of 98% this approach needs to dissipate 5 times more energy than initially required. This method can dissipate the energy up to 26%. It also contains the nonvolatile flip-flop (NVFF) which has energy consumption more when it is used in the functional blocks.

Keywords: Nonvolatile logic, NVFF, STT-MTJ, Nonvolatile test, Scan mechanism.




D. Venkata Prakash, Department of ECE, Aditya College of Engineering & Technology, Surampalem, India; Email: venkataprakas777@gmail.com

Anjaiah Talamala, Department of ECE, Aditya College of Engineering & Technology, Surampalem, India; Email: anjibabu_talamala@acet.ac.in

Mahesh K. Singh*, Department of ECE, Aditya Engineering College, Surampalem, India; Email: mahesh.singh@accendere.co.in

Y. Kuntam Yamini Devi , Department of ECE, Aditya Engineering College, Surampalem, India; Email: yaminideviy@aec.edu.in

    [1] Bishnoi, R., Ebrahimi, M., Oboril, F., & Tahoori, M. B. (2014, October). Read disturb fault detection in STT-MRAM. In 2014 International Test Conference (pp. 1-7). IEEE.[Cross Ref]
    [2] Bishnoi, R., Ebrahimi, M., Oboril, F., & Tahoori, M. B. (2016). Improving write performance for STT-MRAM. IEEE Transactions on Magnetics, 52(8), 1-11.[Cross Ref]
    [3] Koga, M., Iida, M., Amagasaki, M., Ichida, Y., Saji, M., Iida, J., & Sueyoshi, T. (2010, August). First prototype of a genuine power-gatable reconfigurable logic chip with FeRAM cells. In 2010 International Conference on Field Programmable Logic and Applications (pp. 298-303). IEEE.[Cross Ref]
    [4] Wang, Y., Liu, Y., Li, S., Zhang, D., Zhao, B., Chiang, M. F., ... & Yang, H. (2012, September). A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops. In 2012 Proceedings of the ESSCIRC (ESSCIRC) (pp. 149-152). IEEE.[Cross Ref]
    [5] Zhao, W., Belhaire, E., & Chappert, C. (2007, August). Spin-MTJ based non-volatile flip-flop. In 2007 7th IEEE conference on nanotechnology (IEEE NANO) (pp. 399-402). IEEE. [Cross Ref]
    [6] Wang, J., Liu, Y., Yang, H., & Wang, H. (2010, June). A compare-and-write ferroelectric nonvolatile flip-flop for energy-harvesting applications. In The 2010 International Conference on Green Circuits and Systems (pp. 646-650). IEEE. [Cross Ref]
    [7] Kazi, I., Meinerzhagen, P., Gaillardon, P. E., Sacchetto, D., Leblebici, Y., Burg, A., & De Micheli, G. (2014). Energy/reliability trade-offs in low-voltage ReRAM-based non-volatile flip-flop design. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(11), 3155-3164. [Cross Ref]
    [8] Singh, M. K., Singh, A. K., & Singh, N. (2018). Acoustic comparison of electronics disguised voice using different semitones. Int J Eng Technol (UAE), 7(2), 98.[Cross Ref]
    [9] Brundana, M. S. S., Rajeswari, P. S. R., Sravani, N., & Kumar, S. (2021, April). Successive Approximation Compressor for Efficient FIR Filters in C-MOS VLSI Design. In 2021 6th International Conference for Convergence in Technology (I2CT) (pp. 1-4). IEEE.[Cross Ref]
    [10] Anushka, R. L., Jagadish, S., Satyanarayana, V., & Singh, M. K. (2021, October). Lens less Cameras for Face Detection and Verification. In 2021 6th International Conference on Signal Processing, Computing and Control (ISPCC) (pp. 242-246). IEEE.[Cross Ref]
    [11] Singh, M. K., Singh, A. K., & Singh, N. (2018). Disguised voice with fast and slow speech and its acoustic analysis. Int J Pure Appl Math, 118(14), 241-246.[Cross Ref]
    [12] Jyothi, K. D., Sekhar, M. S. R., & Kumar, S. (2021, October). Applications of Statistical Machine Learning Algorithms in Agriculture Management Processes. In 2021 6th International Conference on Signal Processing, Computing and Control (ISPCC) (pp. 237-241). IEEE.[Cross Ref]
    [13] Singh, M. K., Singh, A. K., & Singh, N. (2019). Multimedia analysis for disguised voice and classification efficiency. Multimedia Tools and Applications, 78(20), 29395-29411.[Cross Ref]
    [14] Nandini, A., Kumar, R. A., & Singh, M. K. (2021, October). Circuits Based on the Memristor for Fundamental Operations. In 2021 6th International Conference on Signal Processing, Computing and Control (ISPCC) (pp. 251-255). IEEE.[Cross Ref]
    [15] Santhoshi, M. S., Sharath Babu, K., Kumar, S., & Nandan, D. (2021). An investigation on rolling element bearing fault and real-time spectrum analysis by using short-time fourier transform. In Proceedings of International Conference on Recent Trends in Machine Learning, IoT, Smart Cities and Applications (pp. 561-567). Springer, Singapore.[Cross Ref]
    [16] Singh, M. K., Singh, A. K., & Singh, N. (2019). Multimedia utilization of non-computerized disguised voice and acoustic similarity measurement. Multimedia Tools and Applications, 1-16.[Cross Ref]
    [17] Yang, J., Dengi, A., & Vrudhula, S. (2018). Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic. IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, 26(12), 2628-2640.[Cross Ref]
    [18] Pushkar Praveen and Rakesh Kumar Singh (2022), Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies. IJEER 10(2), 381-386. DOI: 10.37391/IJEER.100253.[Cross Ref]

D. Venkata Prakash, Anjaiah Talamala, Mahesh K. Singh and Y. Kuntam Yamini Devi (2022), Non-Volatile Logic Design Considerations for Energy Efficient Tolerant Variation. IJEER 10(4), 868-871. DOI: 10.37391/IJEER.100419.