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Research Article |

Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module

Author(s): M Nagabushanam1, Skandan Srikanth2, Rushita Mupalla3, Sushmitha S Kumar4 and Swathi K5

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 10, Issue 4

Publisher : FOREX Publication

Published : 15 December 2022

e-ISSN : 2347-470X

Page(s) : 1099-1106

DOI: https://doi.org/10.37391/IJEER.100455

Abstract

The development of Digital Signal Processors (DSPs), graphical systems, Field Programmable Gate Arrays (FPGAs)/ Application-Specific Integrated Circuits (ASICs), and multimedia systems all rely heavily on digital circuits. The need for high-precision fixed-point or floating-point multipliers suitable for Very Large-Scale Integration (VLSI) implementation in high-speed DSP applications is developing rapidly. An integral part of any digital system is the multiplier. In digital systems as well as signal processing, the adder and multiplier seem to be the fundamental arithmetic units. Problems arise when using a multiplier in the realms of area, power, complexity, and speed. This paper details a more efficient MAC (Multiply- Accumulate) multiplier that has been tuned for space usage. The proposed design is more efficient, takes up less room, and has lower latency than conventional designs. The performance of the Additive Multiply Module (AMM) multiplier is measured against that of existing multipliers, where it serves as a module in the MAC reducing area and delay.

Keywords: AMM, Booth Multiplier, Dadda Multiplier, Cadence, MAC.




M Nagabushanam*, Assistant Professor, Department of Electronics and Communication Engineering, M.S Ramaiah Institute of Technology, Bangalore, Karnataka 560054, India; Email: nagabhushanam1971@msrit.edu

Skandan Srikanth, Student, Department of Electronics and Communication Engineering, M.S Ramaiah Institute of Technology, Bangalore, Karnataka, India; Email: skandans4@gmail.com

Rushita Mupalla, Student, Department of Electronics and Communication Engineering, M.S Ramaiah Institute of Technology, Bangalore, Karnataka, India; Email: rushita194@gmail.com

Sushmitha S Kumar, Student, Department of Electronics and Communication Engineering, M.S Ramaiah Institute of Technology, Bangalore, Karnataka, India; Email: sushmikumar8@gmail.com

Swathi K, Student, Department of Electronics and Communication Engineering, M.S Ramaiah Institute of Technology, Bangalore, Karnataka, India; Email: swathikantharajskg@gmail.com

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M Nagabushanam, Skandan S, Rushita M, Sushmitha S Kumar and Swathi K (2022), Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module. IJEER 10(4), 1099-1106. DOI: 10.37391/IJEER.100455.