FOREX Press I. J. of Electrical & Electronics Research
Support Open Access
  • Home/
  • IJEER-100458

Research Article |

VLSI Implementation of Integrated Massive MIMO Systems (IMMS) for N-point FFT/IFFT Processor

Author(s): Kiranmai Babburu1, S S Kiran2, Lavanya Vadda3, K Gurucharan4 and B V R Gowri5

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 10, Issue 4

Publisher : FOREX Publication

Published : 15 December 2022

e-ISSN : 2347-470X

Page(s) : 1121-1129

DOI: https://doi.org/10.37391/IJEER.100458

Abstract

The 5G technologies and OFDM introduce a substantial element of latency in the baseband Massive MIMO system. To declaim the low delay demand of multiple input and multiple outputs, a Fast Fourier Transform (FFT) and also consequent implementation was proposed. The main idea of this proposed system is to utilize the VLSI chip routing technology and reduce computations, processing time, and low latency. This proposed system is to reduce the number of computational complexities in the downlink and reorder the uplink. In OFDM implementation, the chip area of FFTs and IFFTs is occupied by memories, and these memories can be extracted using registers or RAM. An efficient data programming approach for memories and butterflies has been developed using embedded VLSI technology with multiple inputs and outputs (MIMO), known as mass embedded MIMO systems. Using this proposed scheme (Integrated Massive MIMO), N point FFT/IFFT processor design achieves a better throughput and lowest latency than for single-input pipelined FFT or IFFT architectures. In an N-point FFT/IFFT, the introduced scheme using VLSI Technology leads to more reduction in the latency. This N-point FFT/IFFT implementation is named “Integrated Massive MIMO Systems” (IMMS).

Keywords: Integrated Massive MIMO System (IMMS), OFDM, FFT, Latency, N-pt. IFFT/FFT implementation.




Kiranmai Babburu*, Department of ECE, Lendi Institute of Engineering and Technology, Vizianagaram, India; Email: kiranmai.b@lendi.org

S S Kiran, Department of ECE, Lendi Institute of Engineering and Technology, Vizianagaram, India; Email: sskiran88k@gmail.com

Lavanya Vadda, Department of ECE, MVGR college of Engineering, Vizianagaram, India; Email: lavanyavadda@gmail.com

K Gurucharan, Department of ECE, Lendi Institute of Engineering and Technology, Vizianagaram, India; Email: charan.lendi@gmail.com

B V R Gowri, Department of ECE, GVP College of Engineering for Women Visakhapatnam, India; Email: bvr.gowri@lendi.org

    [1] M. Mahdavi et.al, “A Low Latency FFT/IFFT Architecture for Massive Mimo Systems Utilizing OFDM Guard Bands” IEEE Transactions on Circuits and Systems–I Regular Papers 1549-8328 © 2019 IEEE.[Cross Ref]
    [2] Erik G. et. al “Massive MIMO for Next Generation Wireless Systems” IEEE Comm. Mag., vol. 52, no. 2, pp. 186–195, Feb. 2014.[Cross Ref]
    [3] Trung Kien Vu, at.al “Ultra-Reliable and Low Latency Communication in mm Wave-Enabled Massive MIMO Networks” IEEE Communications Letters1089-7798 (c) 2016 IEEE.[Cross Ref]
    [4] Hao Wu, et. al “Analysis of DFT-Based Channel Estimation for Uplink Massive MIMO Systems” IEEE COMMUNICATIONS LETTERS, VOL. 22, NO.2, 2018 1558-2558 © 2017 IEEE.[Cross Ref]
    [5] Francois Rottenberg et.al, Efficient Equalization of Time-Varying Channels in MIMO OFDM Systems- IEEE Transactions on Signal Processing 1053-587X (c) 2019. [Cross Ref]
    [6] Xiliang Luo et.al “A Scalable Framework for CSI Feedback in FDD Massive MIMO Via Dl Path Aligning-IEEE Transactions on Signal Processing 1053-587x (C) 2016 IEEE S.[Cross Ref]
    [7] D. Meenakshi, et. al ‘compare the performance analysis for FFT based MIMO OFDM with dwt-based MIMO-OFDM’ 2013 IEEE (ICECCN 2013)[Cross Ref]
    [8] Akhilesh Venkata Subramanian et.al, ‘’Channel Estimation for A Multi-User MIMOOFDM-IDMA System ‘’ International Conference on Communication and Signal Processing, April 6-8, 2017.[Cross Ref]
    [9] Archana gale ‘’Performance Evaluation of MIMO-OFDM System using MATLAB-Simulink with Real Time Image Input’’ 2013 Tenth International Conference on Wireless and Optical Communications Networks.[Cross Ref]
    [10] Arun Kumar K A ‘’ ARM-FPGA Implementation of a Partially Reconfigurable OFDM-MIMO Phy-Link’’ 2018 International CET Conference on Control, Communication, and Computing (IC4) | July 05 – 07, 2018.[Cross Ref]
    [11] N Kirubanandasarathy et.al’’ VLSI design of mixed radix FFT Processor for MIMO OFDM in wireless communications’’ ICCCCT-10.[Cross Ref]
    [12] Raja jayamaniet.al’’ VLSI implementation of high throughput MlMO OFDM transceivers for 4th generation systems Indian Journal of Engineering and Material Sciences, vol.9, pp. 307- 319, 2012.[Cross Ref]
    [13] Larsson, Erik G.; et.al “Massive MIMO for Next Generation Wireless Systems” IEEE Communications Magazine, 52(2), 186-195. [Cross Ref]
    [14] Shaohan Liu and Dake Liu “A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G” IEEE Transactions on VERY Large-Scale Integration (VLSI) Systems, 2018, 1-13.[Cross Ref]
    [15] Felipe Minotta, et.al “Automated Scalable Address Generation Patterns for 2-Dimensional Folding Schemes in Radix-2 FFT Implementations” Electronics 2018, 7, 33; doi:10.3390/electronics7030033, 1-18.[Cross Ref]
    [16] C. Yu and M.-H. Yen, “Area-efficient 128- to 2048/1536-point pipeline FFT processor for LTE and mobile WiMAX systems,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 9, pp. 1793–1800, Sep. 2015.[Cross Ref]
    [17] ‘Wen-Chang Yeh’ & ‘Chein-Wei Jen’ “High-Speed and Low-Power Split-Radix FFT” IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 51, NO. 3, MARCH 2003, 864-874.[Cross Ref]
    [18] Z Wang, et.al “A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT” IEEE TRANSACTIONS ON (VLSI) SYSTEMS 2013, 1-5pg. [Cross Ref]
    [19] Y N Chang, “Design of an 8192-point Sequential I/O FFT Chip”, World Congress on Engineering and Computer Science 2012 Vol II WCECS 2012, October 24-26, 2012, San Francisco, USA, 1-6pg[Cross Ref]
    [20] K J Yang, Shang Ho T, and Gene C. H. Chuang IEEE Members, MDC FFT/IFFT Processor with Variable Length for MIMO-OFDM Systems.[Cross Ref]
    [21] Anil Kumar Sahu, Vivek Kumar Chandra, G R Sinha, Optimized System Level Hardware Realization of Built-in-Self-Test Approach for Sigma-Delta Analog-to-Digital Converter, International Journal of Electrical and Electronics Research (IJEER), September 30, 2016, Volume 4, Issue 3, Pages: 85-90.[Cross Ref]
    [22] Anil Sufia Banu and Shweta Gupta, Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso, International Journal of Electrical and Electronics Research (IJEER), 30 June 2022, Volume 10, issue 2, Pages : 341-346, DoI: https://doi.org/10.37391/ijeer.100246 [Cross Ref]
    [23] Sarabpreet Kaur, Jyoti Patel, A Robust Image Mosaicing Technique Using Frequency Domain, International Journal of Electrical and Electronics Research (IJEER), Published: March 30, 2018, Volume 6, Issue 1, Pages: 1-8. [Cross Ref]
    [24] K. Gurucharan, B. Kiranmai, S. S. Kiran and M. Ravindra Kumar, Xilinx Based Electronic Voting Machine, International Journal of Engineering and Advanced Technology (IJEAT), October 2019 ISSN: 2249–8958, Volume-9 Issue-1, pg-3935-3939, DOI: 10.35940/ijeat. A1484.109119.[Cross Ref]
    [25] S S Kiran, Mallavarapu Babu, Kiranmai, Babburu & Gurucharan, Kapila. (September 2022). Advanced Wireless Communications for Future Technologies-6G and beyond 6G. 1st Edition, CRC Press, Chapter-1 10.1201/9781003230526-1.[Cross Ref]
    [26] Bylapudi Rama Devi, Babburu Kiranmai, K. Gurucharan, P. Srujana S S Kiran. A Coherent Hybrid Precoding for homogenize Millimetre-wave Multiple- in Multiple- out Systems for 5G Communication Proceedings of the Fifth International Conference on Computing Methodologies and Communication (ICCMC 2021) DVD Part Number: CFP21K25-DVD: ISBN: 978-0-7381- 1204-6/21 © 2021 IEEE. Pages 207-211.[Cross Ref]
    [27] B. Kiranmai, V. Lavanya, and S. S. Kiran. An Energy-Efficient Resource Allocation System Using OFDM DAS Model for LTE Applications. (eds.), Communication Software and Networks, Lecture Notes in Networks and Systems 134, https://doi.org/10.1007/978-981-15- 5397-4_57 © Springer Nature Singapore Pte Ltd. 2021[Cross Ref]
    [28] P Srujana, S.S Kiran, B. Kiranmai, Developing An IDWT-DWT OFDM with AWGN Channel using Differnt Modulation Techniques. JUNI KHYAT ISSN: 2278-4632 Vol-10 Issue-5 NO. 5 May 2020. pg. 69-73.[Cross Ref]
    [29] Kiranmai Babburu, Kapila Gurucharan, S S Kiran, P Srujana, PAPR reduction techniques and image quality assessment in image-based MMS VLC system. IT in Industry, Vol. 9, No.2, 2021, ISSN (Print): 2204-0595 1178- 1185 pgs.[Cross Ref]
    [30] C.-H. Yang, T.-H. Yu, and D. Markovic, “Power and area minimization of reconfigurable FFT processors: A 3GPP-LTE example,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 757–768, Mar. 2012.[Cross Ref]
    [31] X. Y. Shih, H. R. Chou, and Y. Q. Liu, “VLSI design and implementation of reconfigurable 46-mode combined-radix-based FFT hardware architecture for 3GPP-LTE applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 1, pp. 118–129, Jan. 2018.[Cross Ref]

Kiranmai Babburu, S S Kiran, Lavanya Vadda, K Gurucharan and B V R Gowri (2022), VLSI Implementation of Integrated Massive MIMO Systems (IMMS) for N-point FFT/IFFT Processor. IJEER 10(4), 1121-1129. DOI: 10.37391/IJEER.100458.