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Research Article |

Mitigation of Critical Delay in the Carry Skip Adders Using FinFET 18nm Technology

Author(s): Dilshad. Sk1 and Sai Krishna Santosh.G2

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 10, Issue 4

Publisher : FOREX Publication

Published : 30 December 2022

e-ISSN : 2347-470X

Page(s) : 1275-1280

DOI: https://doi.org/10.37391/IJEER.100480

Abstract

In this paper optimization of full adder in 3-dimensional (3-D) using Fin Field Effect Transistor (FinFET) with Gate Diffusion Input (GDI) is proposed to optimize critical delay, power. FinFET technology is more suitable for below 10nm technology process. The major aim of this work is to indemnify significant factor in adder structure i.e. critical delay. Pipelining architecture is enforced to accomplish the objective with the aid of FinFET 18nm technology. The structure is optimized to get the minimum delay confinement. Suggested design needs less logic resources. The outcomes are validated using FPGA synthesis methods. By applying the FinFET technique, we developed adder topology yielding up to 90% performance improvement with respect to delay, power and area compared to the conventional adders. The simulation was carried out with low power cds ff mpt PDK. The study also includes a carry skip adder design for FPGA implementation.

Keywords: FinFET, Critical delay, 8T Full Adder, Carry Skip Adder, FPGA .




Dilshad. Sk*, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Vijayawada, India; Email: skdilshad.ece@gmail.com

Sai Krishna Santosh.G, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Vijayawada, India ; Email: gsksantosh17@gmail.com

    [1] Bagyalakshmi, K. and M. Karpagam. Performance enhancement of efficient process based on Carry-Skip Adder for IoT applications,” Microprocessors and Microsystems 2020.[Cross Ref]
    [2] Kamlapurkar, Sujata.S and Y. Lalitha. “Performance analysis and design of finfet 32 nm based low power, low delay 4-bit ALU, carry save adder and multiplier for high-speed processors,” In: Proc. Of Materials Today, 2020[Cross Ref]
    [3] Tari, Hani Taheri et al. “Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders.” Microelectronic Engineering, 2019.[Cross Ref]
    [4] Radhakrishnan, P & Themozhi, G, FPGA implementation of XOR-MUX full adder-based DWT for signal processing applications, Microprocessors and Micro systems, 2019.[Cross Ref]
    [5] Talha F. Canan;Savas Kaya; Avinash Karanth; Hao Xin, Ahmed Louri, ”Am bipolar SB-FinFET: A New Path to Ultra-Compact Sub-10 nm Logic Circuits,” IEEE Transactions on Electron Devices, Vol. 66,No1,2019.[Cross Ref]
    [6] T. F. Canan, S. Kaya, A. Karanth, H. Xin, and A. Louri, ‘‘Am bipolar SB-FinFET: A new path to ultra-compact sub-10 nm logic circuits,’’ IEEE Trans. Electron Devices, vol. 66, no. 1, pp. 255–263, Jan. 2019. [Cross Ref]
    [7] Bin Talib, G.H., El-Maleh, A.H. & Sait, S.M. “Design of Fault Tolerant Adders,” Arabian Journal of Science and Engineering, Vol. 43, 6667–6692, 2018.[Cross Ref]
    [8] Ch.Rajesh Babu, T Venkatesh, E Jagadeeshwara Rao, “Conventional Full Adder FinFET Implementation using Transmission Gate Logic,” International Journal of Advanced Trends in Computer Science and Engineering, Volume 7, No.6, 2018.[Cross Ref]
    [9] T. N. Theis and H.-S. P. Wong, “The end of Moore’s law: A new beginning for information technology,” Computer. Sci. Eng., vol. 19, no. 2, pp. 41–50, Mar./Apr. 2017.[Cross Ref]
    [10] S. Sanjay. ‘‘Dual Material Pile Gate Approach for low leakage FINFET”, International Journal of Technology, Vol.8, No1, pp.1-4, 2017.[Cross Ref]
    [11] M. Bahadori, M. Kamal, A. Afzali-Kusha and M. Pedram, "High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels," IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 421-433, 2016.[Cross Ref]
    [12] R. F.G. Pikus and A. Torres, “Advanced multi-patterning and hybrid lithography techniques.” In: Proc. of the Asia and South Pacific Design Automation Conference, pp. 611-616, 2016. [Cross Ref]
    [13] H. Yaegashi, “Pattern fidelity control in multi-patterning towards 7 nm node.” In: Proc. of International Conf. Nano technology, Japan, pp. 22-25, 2016.[Cross Ref]
    [14] De Rose, R., Lanuzza, M., Frustaci, F. et al. Designing “Dynamic Carry Skip Adders: Analysis and Comparison” Circuits Systems and Signal Processing, Vol.33, pp. 1019–1034 2014.[Cross Ref]
    [15] Yang, K. Niraj et al., ‘‘FinPrin: FinFET Logic Circuit Analysis and Optimization under PVT Variations”, IEEE Transactions on very large-scale integration (VLSI) Systems, vol. 22, no. 12, 2014.[Cross Ref]
    [16] N. Collaert (ed.), CMOS Nano electronics, Pan Stanford Publishing, Singapore, 2013. [Cross Ref]
    [17] C. Auth, C. Allen, A. Blattner, et al., “A 22-nm-high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors.” In: Symposium on VLS Technology, pp. 131–132, 2012.[Cross Ref]
    [18] K.J. Kuhn, “Considerations for ultimate CMOS scaling,” IEEE Transactions on Electron Devices, Vol 59, No 7, pp. 1813–1828, 2012.[Cross Ref]
    [19] W. Liu, “BSIM4 and MOSFET Modelling for IC Simulation, World Scientific, Singapore, 2011.[Cross Ref]
    [20] S.K. Saha, M.J. Deen, and H. Masuda, “Compact interconnect models for gigascale integration,” IEEE Transactions on Electron Devices, Vol. 56, No 9, pp. 1784–1786, 2009. [Cross Ref]
    [21] M.V. Dunga, “Nanoscale CMOS modelling” Ph.D. dissertation, Electrical Engineering and Computer Science, University of California, Berkeley, CA, 2008.[Cross Ref]
    [22] M.V. Dunga, C.-H. Lin, X. Xi, et al., “Modeling advanced FET technology in a com pact model,” IEEE Transactions on Electron Devices, Vol. 53, No 9, pp. 1971–1978, 2006. [Cross Ref]
    [23] Y. S. Lin and D. Radhakrishnan, "Delay Efficient 32-bit Carry-Skip Adder," In: Proc. of IEEE International Conference on Electronics, Circuits and Systems, pp. 506-509, 2006. [Cross Ref]
    [24] J. Sallese, F. Krummenacher, F. Pregaldiny, et al., “A design-oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism,” Solid-State Electronics, Vol. 49, No 3, pp. 485–489, 2005. [Cross Ref]
    [25] Y. Taur, X. Liang, W. Wang, and H. Lu, A continuous, analytic drain current model for DGMOSFETs”, Vol. 25,2004.[Cross Ref]
    [26] X. Liang and Y. Taur, “A 2-D analytical solution for SCEs in DG MOSFETs,” IEEE Transactions on Electron Devices, Vol. 9, No 51, pp. 1385–1391, 2004.[Cross Ref]

Dilshad. Sk and Sai Krishna Santosh. G (2022), Mitigation of Critical Delay in the Carry Skip Adders Using FinFET 18nm Technology. IJEER 10(4), 1275-1280. DOI: 10.37391/IJEER.100480.