Research Article |
Performance Analysis of Variable Threshold Voltage (ΔVth) Model of Junction less FinTFET
Author(s): Ajaykumar Dharmireddy1* and Sreenivasarao Ijjada2
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 11, Issue 2
Publisher : FOREX Publication
Published : 30 May 2023
e-ISSN : 2347-470X
Page(s) : 323-327
Abstract
The work presented in this paper is a variable threshold voltage (ΔVth) model of junction less fin gate tunnel FET (JL FinTFET) in which there is a shift in threshold voltage. As a result, to improve drive current and subthreshold slope among other devices. At the same time, gradually decrease the random dopant fluctuations (RDF) effects on Vth, ambipolar leakage current by using this design. The threshold voltage in the junction less fin gate TFET may be modified using 2D numerical simulations by supplying a voltage to the variable gate. The effects of the threshold voltage change on the device's overall performance investigate. A GaSb junction less fin gate TFET and AlGaSb junction less fin gate TFETs with variable threshold voltage characteristics compare. The ON state current is 1.5x10-3 A/m, the SS is 17.1 mV/decade, and the Iamb is 3.314x10-17 A/m.
Keywords: Variable threshold voltage (ΔVth)
, JL Fin FET
, drive current
, ambipolar current
.
Ajaykumar Dharmireddy*, Department of Electronics and Communication Engineering, GITAM (Deemed to be University) Visakapatanam, India; Email: ajaybabuji@gmail.com
Sreenivasarao Ijjada, Department of Electronics and Communication Engineering, GITAM (Deemed to be University) Visakapatanam, India; Email: sijjada@gitam.edu
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[1] T.K.Mohan, DKim, S.R.Nathan, "DoubleGate Strained-Ge Hetero structure TFET With record high drive currents and 60mV/dec subthreshold slope," IEEE International electron devices meeting, PP.1-3, Dec.2008. [Cross Ref]
-
[2] A.G.nudi, S. Reggiani, "Analysis of threshold voltage variability due to random dopant fluctuations in JL FETs," IEEE electron device lett., vol. 33, PP.336-338, 2012. [Cross Ref]
-
[3] Umesh Dutta, M.K. Soni and ManishaPattanaik, "Design and Analysis of TFET for Low Power High-Performance Applications," IJ Modern Edu. and Comp. Science, no.1, PP.65-73, 2018.
-
[4] BLu, HLu, Yu.Zhang, Yizhang, X. Cui, ZhijunLv, "A Charge-Based Capacitance Model for DG TFETs With Closed-Form Solution," IEEE Trans. on electron devices, vol. 65, no. 1, Jan.2018.
-
[5] WYChoi, BG.Park, JDLee, and TJLiu, "TFETs with SS less than 60 mV/dec," IEEE Electron. Device Lett., vol. 28, no. 8, pp. 743–745, Aug. 2007. [Cross Ref]
-
[6] Ajaykumar Dharmireddy, Ijjada S.R "A Novel Design of SOI-based Fin Gate TFET" 2021 IEEE Conference on GCAT, Bangalore, India. Nov.2021. [Cross Ref]
-
[7] Devi N, Ajaykumar Dharmireddy "Performance Analysis of Double Gate Hetero Junction Tunnel Fet" IJITEE, Volume-9, no.3, PP.232-234, Dec. 2019. [Cross Ref]
-
[8] A. Devi N, Ajaykumar Dharmireddy "Doping and Dopingless III-V Tunnel FETs: Investigations on reasons for ON-current improvement" International Conf. on Recent challenges in Engg. Science and Technology,2021.
-
[9] S, Ijjada S.R, Sharma A, Babu M.S,Ajaykumar Dharmireddy "SS <30mV/dec; Hybrid Tunnel FET 3D Analytical Model for IoT applications" Materials Today: Proceedings., 2020. [Cross Ref]
-
[10] Ajaykumar Dharmireddy, Sreenivasa Rao Ijjada, I.Hemalatha, CH.Madhava Rao" Surface Potential Model of Double Metal Fin Gate Tunnel FET" Mathematical Statistician and Engineering Applications, Vol.71 issue no.3, pp. 1044–1060, 2022. [Cross Ref]
-
[11] KaishenOu, Chunxiang Zhu "Germanium Fin Tunnel Field Effect Transistor with Abrupt Tunnel Junction and Large Tunneling Area" IEEE Trans. Electron Devices, vol. 59, no. 2 pp. 292-301, 2018.
-
[12] Jang Woo Lee and Woo Young Choi "Triple-gate Tunnel FETs Encapsulated with an EpitaxialLayer for High Current Drivability" Journal Of Semiconductor Technology And Science, VOL.17, NO.2, APRIL, 2017,https://doi.org/10.5573/JSTS.2017.17.2.271
-
[13] Jang Hyun Kim, Hyun Woo Kim, Garam Kim, Sangwan Kim, and Byung-Gook Park, "Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain" Micromachines 2019, 10, 30; doi:10.3390/mi10010030. [Cross Ref]
-
[14] Pankaj Kumar, Saurav Roy, and SrimantaBaishya "Gate-overlapped-source Heterojunction Tunnel Tri-gate FinFET "Devices for Integrated Circuits, PP.23-24 March 2017, IEEE.PP.561-564. [Cross Ref]
-
[15] S.Blaeser, S.Glass "Novel SiGe/Si line tunnelling TFET with high Ion at low Vdd and constant SS" IEEE international electron devices meeting, December 2015. [Cross Ref]
-
[16] Ajaykumar Dharmireddy, Srinivasa Rao Ijjada, Murthy P.H.S.T, “Performance analysis of 3G SOI FinFET structure with various fin heights using TCAD simulations”, Journal of Advanced Research in Dynamical and Control Systems,11(2), pp-1291-1298, 2019.
-
[17] S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, "Ge-source tunnel field-effect transistors with record high ION/IOFF," in VLSI Symp. Tech. Dig., 2009, pp. 178–179.
-
[18] P. F. Wang et al., "Complementary tunnelling transistor for low power application," Solid-State Electron., vol. 48, no. 12, pp. 2281–2286, Dec. 2004.
-
[19] K. Boucart and A. M. Ionescu, "Double gate tunnel FET with high K gate dielectric," IEEE Trans. Electron Devices, vol. 54, no. 7, pp. 1725–1733, Jul. 2007. [Cross Ref]
-
[20] Borman, G. 2005. An extensive empirical study of feature selection metrics for text classification. J. Mach. Learn. Res. 3 (Mar. 2003), 12810-1305.
-
[21] Brown, L. D., Hua, H., and Gao, C. 2003. A widget framework for augmented interaction in SCAPE.
-
[22] Y.T. Yu, M.F. Lau, "A comparison of MC/DC, MUMCUT and several other coverage criteria for logical decisions", Journal of Systems and Software, 2002, in press. [Cross Ref]
-
[23] Ajaykumar Dharmireddy, Sreenivasa Rao Ijjada , “Steeper Slope Characteristics of DM FINTFET” European Chemical Bulletin, Vol.12 issue no.1,pp. 1312–1321, 2023. [Cross Ref]
-
[24] Ajaykumar Dharmireddy, Dr Sreenivasa Rao Ijjada,I.Hemalatha “Performance analysis of various Fin patterns of hybrid Tunnel FET”1st International Journal of Electrical and Electronics Research , Vol.10 issue no.4,pp. 806–810, 2022. [Cross Ref]
-
[25] Ajaykumar Dharmireddy, Sreenivasarao Ijjada “A Recent Progress of Gate-Source over Lapping Line-TFET” Telematique, Vol.22 issue no.1,pp. 253–264, 2023.
-
[26] Ajaykumar Dharmireddy, SreenivasaRaoIjjada “Design of Low Voltage-Power: Negative capacitance Charge Plasma FinTFET for AIOT Data Acquisition Blocks” 2022 International Conference on Breakthrough in Heuristics and Reciprocation of Advanced Technologies (BHARAT), IEEE conference, 1st -3rd April 2022. [Cross Ref]