FOREX Press I. J. of Electrical & Electronics Research
Support Open Access
  • Home/
  • IJEER-110238

Research Article |

Design of Three-valued Logic Based Adder and Multiplier Circuits using Pseudo N-type CNTFETs

Author(s): K. Maheswari1, M. L. Ravi Chandra2, D. Srinivasulu Reddy3 and V. Vijaya Kishore4*

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 11, Issue 2

Publisher : FOREX Publication

Published : 30 June 2023

e-ISSN : 2347-470X

Page(s) : 518-522

DOI: https://doi.org/10.37391/ijeer.110238

Abstract

This work presents a novel technique to develop the three-valued logic (TVL) circuit schematics for very large-scale integration (VLSI) applications. The TVL is better alternative technology over the two-valued logic because it provides decreased interconnect connections, fast computation speed and decreases the chip complexity. The TVL based complicated designs such as half-adder and multiplier circuits are designed utilizing the Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The proposed TVL half adder multiplier schematics are developed in HSPICE tool. Additionally, the delay and circuit area for the half- adder and multiplier circuits are investigated and compared to the complementary circuits. The memory usage and CPU time for the proposed circuits are also analyzed. It is observed that the proposed circuit designs show the improved performance up to 43.03% on an average over the complementary designs.

Keywords: VLSI, Ternary logic, CNTFET, Pseudo N-type CNTFET, HSPICE.




K. Maheswari, G. Pullaiah College of Engineering and Technology, Kurnool, India

M. L. Ravi Chandra, Srinivasa Ramanujan Institute of Technology, Ananthapuramu, India

Srinivasulu Reddy, S V College of Engineering, Tirupati, India

V. Vijaya Kishore*, Mohan Babu University (erstwhile SreeVidyanikethan Engineering College), Tirupati, India;Email: kishiee@rediffmail.com

    [1] Madhuri, B. D.; Sunithamani, S. Design of Ternary Logic Gates and Circuits using GNRFETs. IET Circuits, Devices & Systems 2020, 14, 972-979. [Cross Ref]
    [2] Gadgil, S.; Vudadha, C. Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach. IEEE Transactions on Nanotechnology 2020, 19, 661-671. [Cross Ref]
    [3] Karmakar, S.; Chandy, J. A.; Jain, F. C. Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2013, 21, 793-806. [Cross Ref]
    [4] Begum, A. Y.; Balaji, M.; Satyanarayana, V. Quantum Dot Cellular Automata using a One-bit Comparator for QCA Gates. Materials Today: Proceeding 2022, 66, 3539-3549. [Cross Ref]
    [5] Nesa, R. P. M.; Thangkhiew, P. L. A Review on Fundamentals of Ternary Reversible Logic Circuits. 2020 International Conference on Computational Performance Evaluation (ComPE), 2020, 738-743. [Cross Ref]
    [6] Wu, G.; Cai, L. Ternary Multiplier of Multigate Single Electron Transistor: Design using 3-T Gate. IEEE ICCA 2010, 1567-1571. [Cross Ref]
    [7] Lin, S.; Kim, Y. -B.; Lombardi, F. CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits. IEEE Transactions on Nanotechnology 2011, 10, 217-225. [Cross Ref]
    [8] Lin, S.; Kim, Y. -B.; Lombardi, F. Design of a Ternary Memory Cell Using CNTFETs. IEEE Transactions on Nanotechnology 2012, 11, 1019-1025. [Cross Ref]
    [9] Zarandi, A. D.; Reshadinezhad, M. R.; Rubio, A. A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells. IEEE Access 2020, 8, 58585-58593. [Cross Ref]
    [10]Kim, S.; Lee, S. -Y.; Park, S.; Kim, K. R.; Kang, S. A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits. IEEE Transactions on Circuits and Systems I: Regular Papers 2020, 67, 3138-3151. [Cross Ref]
    [11] Madhuri, B. D.; Sunithamani, S.; Basha, S. J.; Kumar, V. R. Design of Hardened Flip-flop using Schmitt Trigger based SEM Latch in CNTFET Technology. Circuit World 2020, 47. [Cross Ref]
    [12] Lin, S.; Kim, Y.; Lombardi, F. A Novel CNTFET based Ternary Logic Gate Design. 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, Cancun, Mexico, 2009. [Cross Ref]
    [13] Sahoo, S. K.; Akhilesh, G.; Sahoo, R.; Muglikar, M. High-Performance Ternary Adder Using CNTFET. IEEE Transactions on Nanotechnology 2017, 16, 368-374. [Cross Ref]
    [14] Sridharan, K.; Gurindagunta, S.; Pudi, V. Efficient Multiternary Digit Adder Design in CNTFET Technology. IEEE Transactions on Nanotechnology 2013, 12, 283-287. [Cross Ref]
    [15] Jaber, R. A.; Kassem, A.; El-Hajj, A. M.; El-Nimri, L. A.; Haidar, A. M. High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits. IEEE Access 2019, 7, 93871-93886. [Cross Ref]
    [16] Vudadha, C.; Srinivas, M. B. Design of High-Speed and Power-Efficient Ternary Prefix Adders Using CNFETs. IEEE Transactions on Nanotechnology 2018, 17, 772-782. [Cross Ref]
    [17] Sridevi, V.; Jayanthy, T. Minimization of CNTFET Ternary Combinational Circuits using Negation of Literals Technique. Arabian Journal of Science and Engineering 2014, 39, 4875-4890. [Cross Ref]
    [18] Fereshteh, J.; Paiman, K. Low-power Consumption Ternary Full Adder based on CNTFET. IET Circuits, Devices & Systems 2016, 10, 365-374. [Cross Ref]
    [19] Liang, J.; Chen, L.; Han, J.; Lombardi, F. Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs. IEEE Transactions on Nanotechnology 2014, 13, 695-708. [Cross Ref]
    [20] Deng, J.; Wong, H.-S. P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and its Application—Part I: Model of the Intrinsic Channel Region. IEEE Trans. Electron Device 2007, 54, 3186–3194. [Cross Ref]
    [21] Deng, J.; Wong, H.-S. P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and its Application—Part II: Full Device Model and Circuit Performance Benchmarking. IEEE Trans. Electron Device 2007, 54, 3195–3205. [Cross Ref]

K. Maheswari, M. L. Ravi Chandra, D. Srinivasulu Reddy and V. Vijaya Kishore (2023), Design of Three-valued Logic Based Adder and Multiplier Circuits using Pseudo N-type CNTFETs. IJEER 11(2), 518-522. DOI: 10.37391/IJEER.110238.