Research Article |
Design and Implementation of a Bootstrap-based Sample and Hold Circuit for SAR ADC Applications
Author(s): Chakradhar Adupa* and Sreenivasarao Ijjada
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 11, Issue 3
Publisher : FOREX Publication
Published : 10 August 2023
e-ISSN : 2347-470X
Page(s) : 689-695
Abstract
The resolution and conversion speed of an Analog to Digital converter (ADCs) strongly depends on how efficiently Sampling and Hold (S&H) circuit handles the amplitude skewing of the input analog signal. In this article, a novel S&H circuit has been proposed to handle the errors produced because of amplitude skewing. This circuit has two different paths for sampling and holds process and avoids the non-ideal effects seen in most of the recent literature. In portable applications, the restrictions on the available power and the importance of the quality of digital data are taken as a challenge. To make SAR-ADC more power efficient, all blocks should be designed with low-power techniques. Here, the sample and hold block need to be designed to the optimized power level, operate supply of 3.3V, implemented with SCL 0.18µm process, operating at a sampling rate of 10MHz with the power of 0.425mW.
Keywords: Analog to Digital Converter (ADC)
, Digital to Analog Converter (DAC)
, Successive Approximation Register SAR
, Mega Sample Per Second (MSPS)
, Signal to Noise Distortion Ratio (SNDR)
.
Chakradhar Adupa*, Department of Electrical Electronics and Communication Engineering, GITAM (Deemed to be University), Visakhapatnam, India; Email: chakradhar.a@sru.edu.in
Sreenivasarao Ijjada, Department of Electrical Electronics and Communication Engineering, GITAM (Deemed to be University), Visakhapatnam, India; Email: sijjada@gitam.edu
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