Research Article |
Performance Enhancement of CNFET-based Approximate Compressor for Error Resilient Image Processing
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 11, Issue 3
Publisher : FOREX Publication
Published : 28 September 2023
e-ISSN : 2347-470X
Page(s) : 851-858
Abstract
The approximate computing has emerged as an appealing approach to minimize energy consumption. By implementing inexact circuits at the transistor level, significant enhancements in various performance metrics such as power consumption, delay, energy, and area can be achieved. Consequently, researchers worldwide have been actively exploring the application of inexact techniques in circuit design. This paper introduces a novel technique for designing low-power digital circuits called extremely low power modified gate diffusion input (ELP-MGDI). This technique combines the principles of Modified Gate Diffusion Input with the utilization of Carbon Nano Tube Field-Effect Transistors (CNTFETs). The Objective of this paper is to enhance the power, delay, and area characteristics of a 4:2 compressor and multiplier by employing ELP-MGDI approach. To achieve this, we conducted thorough analysis and simulations using the Verilog-A simulator 32 nm CNFET technology Stanford University within the Cadence Virtuoso Tool. The results show extremely power, delay reduction and power-delay-product (PDP) of approximate multiplier has been improved by over 99%, and the circuit area has been reduced by 55%. The proposed processing module demonstrates superior performance compared to their conventional counterparts.
Keywords: MGDI
, ELP-MGDI
, Approximate Compressor
, Approximate multiplier
, CNFET
, CMOS
.
Siliveri Swetha*, ECE Department, CVR College of Engineering, Hyderabad, India; Email: siliveriswetha.cvr@gmail.com
Dr.N. Siva Sankara Reddy, ECE Department, Vasavi College of Engineering, Hyderabad, India; Email: nssreddy69@gmail.com
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[1] M. Ha, S. Lee, “Multipliers with approximate 4–2 compressors and error recovery modules” IEEEEmbed. Syst. Lett. 10(1), 6–9 (2018)., https ://doi.org/10.1109/LES.2017.27460 84.
-
[2] F. Sabetzadeh, M.H. Moaiyeri, M. Ahmadinejad, “A majority-based imprecise multiplier for ultraefficient approximate image multiplication” IEEE Trans. Circuits Syst. I Regul. Pap. 66(11), 4200–4208 (2019),https ://doi.org/10.1109/TCSI.2019.29182 41.
-
[3] C.H. Chang, J. Gu, M. Zhang, “Ultra low-voltage low-power CMOS 4–2 and 5–2 compressors for fast arithmetic circuits” IEEE Trans.CircuitsSyst.IRegul.Pap.51(10), 1985–1997(2004) https:// doi.org/10.1109/TCSI.2004.83568 3.
-
[4] V. Leon, G. Zervakis, S. Xydis, D. Soudris, K. Pekmestzi, “Walking through the energy-error Paretofrontier of approximate multipliers” IEEE Micro 38(4), 40–49 (2018),https ://doi.org/10.1109/MM.2018.04319 1124.
-
[5] Salmanpour, F., Moaiyeri, M.H. & Sabetzadeh, F. “Ultra-Compact Imprecise 4:2 Compressor and Multiplier Circuits for Approximate Computing in Deep Nanoscale” Circuits Syst Signal Process 40, 4633–4650 (2021), https://doi.org/10.1007/s00034-021-01688-8.z.
-
[6] N.H.E. Weste, K. Eshraghian, “Principles of CMOS VLSI Design: A System Perspective (Addison-Wesley,Reading, 1988).
-
[7] J. Lin, Y. Hwang, M. Sheu, C. Ho, “A novel high-speed and energy efficient 10-transistor full adder design” IEEE Trans. Circuits Syst. I 54(5), 1050–1059 (2007).
-
[8] M. Aalelai Vendhan,”Analysis on Circuit Metrics of 1-Bit FinFET Adders Realized using Distinct Logic Structures” Indian Journal of Science and Technology, 2019, Volume: 12, Issue: 26, Pages: 1-4,DOI: 10.17485/ijst/2019/v12i26/145499.
-
[9] R. Uma, P. Dhavachelvan, Modified Gate Diffusion Input Technique: “A New Technique for Enhancing Performance in Full Adder Circuits”, Procedia Technology, Volume 6,2012, Pages 74-81,ISSN 2212-0173,Available from :https://doi.org/10.1016/j.protcy.2012.10.010
-
[10] Y. S. Mehrabani, and M. Eshghi, “High-speed, high frequency and low-PDP, CNFET full adder cells”, J.Circuits Syst .Comput., Vol. 24, pp. 1–24, 2015, https://doi.org/10.1142/S021-8126615501303.
-
[11] Rahman, L. Guo, S. Datta, and M. S. Lundstrom,“Theory of ballistic nanotransistors, IEEE Trans. Electron Devices, Vol. 50, pp. 1853–1864, 2003. https://doi.org 10.1109/TED.2003.815366.
-
[12] Elmira Tavakkoli, Shayan Shokri & Mahdi Aminian (2023)” Comparison anddesign of energy-efficient approximate multiplier schemes for image processing by CNTFET”, International Journal of Electronics, https://doi.org /10.1080/00207217.2023.2192968.
-
[13] Rishika Sethi, Gaurav Soni (2016)” Comparative Analysis of Si-MOSFET and CNFET-Based 28T Full Adder”. In: Pant, M., Deep, K., Bansal, J., Nagar, A., Das, K. (eds) Proceedings of Fifth International Conference on Soft Computing for Problem Solving. Advances in Intelligent Systems and Computing, vol 436. Springer, Singapore. Available from:https://doi.org/10.1007/978-981-10-0448-3_36.
-
[14] Pishvaie A, Jaberipur G, Jahanian A (2014) “High-performance CMOS (4:2) compressors” Int J Electron 101(11):1511–1525.
-
[15] Arasteh, M.H. Moaiyeri, M.R. Taheri, K. Navi, N. Bagherzadeh, “An energy and area efficient4:2 compressor based on FinFETs” Integration 60, 224–231 (2018). Available from:https ://doi.org/10.1016/j.vlsi.2017.09.010.
-
[16] Gorantla, A. (2017). “Design of approximate compressors for multiplication”, ACM Journal on EmergingTechnologies in Computing Systems (JETC), 13(3), 1–17. Available from, https://doi.org/10.1145/3007649.
-
[17] Shirinabadi Farahani, S., & Reshadinezhad, M. R. (2019). “A new twelve-transistor approximate 4: 2compressor in CNTFET technology”, International Journal of Electronics, 106(5), 691–706.,https://doi.org/10.1080/00207217.2018.1545930.
-
[18] Reddy, K. M., Vasantha, M. H., Kumar, Y. N., & Dwivedi, D. (2019).” Design and analysis of multiplier using approximate 4-2 compressor”, AEU-International Journal of Electronics and Communications,107, 89–97. Available from:https://doi.org/10.1016/j.aeue.2019.05.021.
-
[19] Venkatachalam, S., & Ko, S. B. (2017). “Design of power and area efficient approximate multipliers” IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, 25(5), 1782–1786. https://doi.org/10.1109/TVLSI.2016.2643639.
-
[20] Baran D, Aktan M, Oklobdzija VG (2010)” Energy efficient implementation of parallel CMOS multipliers with improved compressors.” ACM/IEEE international symposium on low-powerelectronics and design (ISLPED), pp 147–152.
-
[21] Momeni, J. Han, P. Montuschi, F. Lombardi, “Design and analysis of approximate compressors for multiplication” IEEE Trans. Comput. 64(4), 984–994 (2015). Available from: https ://doi.org/10.1109/TC.2014.23082 14.
-
[22] M. Ahmadinejad, M.H. Moaiyeri, F. Sabetzadeh, “Energy and area efficient imprecise compressors for approximate multiplication at nanoscale”, Int. J. Electron. Commun. 110, 152859 (2019). https ://doi.org/10.1016/j.aeue.2019.15285 9.
-
[23] Z. Yang, J. Han and F. Lombardi, “Approximate compressors for error-resilient multiplier design, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems”, (DFTS), Amherst, MA, USA, 2015, pp. 183-186, doi: 10.1109/DFT.2015.7315159.
-
[24] Eamani, R. R. ., & Kumar, N. V. . (2023). Design and Analysis of Multiplexer based Approximate Adder for Low Power Applications. International Journal on Recent and Innovation Trends in Computing and Communication, 11(3), 228–233.
-
[25] Sayadi, L and Timarchi, S and Sheikh Akbari, A (2023) Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors. IEEE Transactions on Circuits and Systems Part 1: Regular Papers. pp. 1-11. ISSN 1549-8328 DOI:https://doi.org/10.1109/TCSI.2023.3242558.