I. J. of Electrical & Electronics Research
Research Article | 
A Compact Hardware Design and Implementation on FPGA Based Hybrid of AES and Keccak SHA3-512 for Enhancing Data Security
Author(s): K Janshi Lakshmi and G Sreenivasulu
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 12, Issue 1
Publisher : FOREX Publication
Published : 15 march 2024
e-ISSN : 2347-470X
Page(s) : 195-202
Abstract
Data security means protecting important information from unauthorised persons. In a security system, cryptography is the most secure method. Cryptography has many kinds, but the Advanced Encryption Standard (AES) is the most secure system. If combined with AES and Secure Hash Algorithm-3-512Bits (SHA3-512), it becomes compact, more secure, and more authenticated for data communications. The proposed methodology is a hybrid cryptography technique that combines AES with the SHA3-512 algorithm. This system becomes a strong, secure system and produces a strong cipher text. The proposed method AES/SHA3-512 is Hardware implementation on the Artix-7 FPGA family yields the lowest cost and highest hardware efficiency with a reduction in area usage of LUT 18.49%, Flip Flops 0.83%, and IO 3.8%. The proposed architecture is synthesised and simulated using the Vivado 2017.2 version Tool.
Keywords: Data Security, Cryptography, AES, Keccak SHA3-512, FPGA Artix-7, Vivado.
K Janshi Lakshmi*, Research Scholar (Full Time), Department of Electronics and Communication Engineering, Sri Venkateswara University, Tirupati, AndhraPradesh, India; Email: jansikaramala@gmail.com
G Sreenivasulu, Professor, Department of Electronics and Communication Engineering, Sri Venkateswara University, Tirupati, AndhraPradesh, India; Email: gunapatieee@rediffmail.com
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