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Research Article |

Exact Computing Multiplier Design using 5-to-3 Counters for Image Processing

Author(s): Perumal B, Balamanikandan A*, Jayakumar S, Ashok Kumar N and Saranya K

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 12, Issue 2

Publisher : FOREX Publication

Published : 30 April 2024

e-ISSN : 2347-470X

Page(s) : 435-442

DOI: https://doi.org/10.37391/IJEER.120215

Abstract

This work presents a novel approach to improve the area and energy efficiency of 5:3 counter, a key element used in digital arithmetic. To provide an effective substitute for addition operations, mostly in the partial product reduction stage of larger multipliers, this study suggests a new 5:3 counter. The Input Shuffling Unit (ISU) is employed within the proposed 5:3 counter to minimize gate-level implementation and path delay during partial product reduction in 16-bit and larger multipliers, thereby enhancing area and energy efficiency. Consequently, there are 84% fewer choices of input-output combinations, thereby decreasing the circuit complexity with respect to area and energy usage. When compared to its existing counterparts, the suggested 5:3 compressor improves area utilization and energy usage by an average of 11%, 17%, and 17% in 8-, 16-, and 32-bit multipliers, respectively. The results of simulations demonstrate the superiority of our method over traditional designs, providing an increase in both area and energy efficiency. These results highlight the applicability and scalability of our method, which is appropriate for a variety of applications such as embedded systems and digital signal processing.

Keywords: 5:3 Counter, Multiplier design, Area and energy optimization, Input shuffling unit.




Perumal B, Electrical and Electronics Engineering, Adhiyamaan College of Engineering, Hosur, India; Email: perumalbalan7@gmail.com

Balamanikandan A*, Electronics and Communication Engineering, Mohan Babu University (Erstwhile SreeVidyanikethan Engineering College), Tirupati, India; Email: balamanieee83@gmail.com

Jayakumar S, Electronics and Communication Engineering, Sri Sairam College of Engineering, Bengaluru, India; Email: jayakmr1982@gmail.com

Ashok Kumar N, Electronics and communication engineering, Mohan Babu University (Erstwhile SreeVidyanikethan Engineering College), Tirupati, India; Email: ashoknoc@gmail.com

Saranya K, Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, India; Email: saranya@drmcet.ac.in

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Perumal B, Balamanikandan A, Jayakumar S, Ashok Kumar N and Saranya K (2024), Exact Computing Multiplier Design using 5-to-3 Counters for Image Processing. IJEER 12(2), 435-442. DOI: 10.37391/IJEER.120215.