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Research Article |

Optimizing Configurable Logic Blocks with Advanced Error-Resilient Circuits for Low-Power FPGA Systems

Author(s): Dankan Gowda V.1*,Sampada Abhijit Dhole2, KDV Prasad3, Jayamala Kumar Patil4, S.M. Jagdale5, Shaik Farook6, Dipti Sakhare7

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 13, Issue 2

Publisher : FOREX Publication

Published : 30 May 2025

e-ISSN : 2347-470X

Page(s) : 227-236

DOI: https://doi.org/10.37391/IJEER.130206

Abstract

This paper aims at enhancing configurable logic blocks (CLBs) in FPGA systems through incorporating more complex error-tolerant circuits and power control strategies. The architecture of the Presented FPGA considered in this study has been designed using MATLAB simulation and is tailored for low power consumption and high reliability. Power management is another feature implemented in the system through Dynamic Voltage Scaling (DVS) to improve electrical power usage essentially by 20%-25% at low load”. The fault tolerance is implemented through incorporating ECC and TMR into CLBs to render the system capable of tolerating with faults and still work efficiently. Among the results of the simulation, 95% of fault types that were produced are detected and it has an MTBF of 6000 hours, which indicates that the system of fault detection is a reliable one. The same applies to the proposed design, which signifies that the power consumption only increases by 10-15% when the number of CLBs is expanded to 1000. If compared with Xilinx Virtex-7 and Intel Arria 10 FPGA architectures the suggested system contributes to 30% higher MTBF and 20% power reduction which give it more reliability and efficiency.

Keywords: FPGA, Configurable Logic Blocks, Low-Power Systems, Error-Resilient Circuits, Fault-Tolerant Design, Power Optimization, Reliability, MATLAB, Simulation.




Dankan Gowda V.,Department of Electronics and Communication Engineering, BMS Institute of Technology and Management, Bangalore, Karnataka, India;Email: dankan.v@bmsit.in

Sampada Abhijit Dhole,Assistant Professor, Department of Electronics and Telecommunication Engineering, Bharati Vidyapeeth’s College of Engineering for Women, Pune, Maharashtra, India; Email: sampada.dhole@bharatividyapeeth.edu

KDV Prasad, Department of Research, Symbiosis Institute of Business Management, Hyderabad, Symbiosis International (Deemed University) Pune, India; Email: Kdv.prasad@sibmhyd.edu.in

Jayamala Kumar Patil, Associate Professor, Department of Electronics and Telecommunication Engineering, Bharati Vidyapeeth’s College of Engineering, Kolhapur, Maharashtra, India; Email: jayamala.p@rediffmail.com

S.M. Jagdale, Assistant Professor, Department of Electronics and Telecommunication Engineering, Bharati Vidyapeeth’s College of Engineering for Women, Pune, Maharashtra, India; Email: sumatijagdale@gmail.com

Shaik Farook, Professor, Department of EEE, School of Engineering Mohan Babu University Tirupati-517 102, India; Email: farook.208@gmail.com

Dipti Sakhare, Professor, Department of Electronics and Telecommunication Engineering, MIT Academy of Engineering Alandi Pune, Pune, Maharashtra, India; Email: diptiysakhare@gmail.com

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Dankan Gowda V., Sampada Abhijit Dhole, KDV Prasad, Jayamala Kumar Patil, S.M. Jagdale, Shaik Farook, and Dipti Sakhare (2025), Optimizing Configurable Logic Blocks with Advanced Error-Resilient Circuits for Low-Power FPGA Systems. IJEER 13(2), 227-236. DOI: 10.37391/IJEER.130206.