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Research Article |

Design and Simulation of a Quaternary Logic Gate Using a Universal Spatial Wavefunction Switched Field-Effect Transistor NOR Gate

Author(s): Bander Saman1*

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 13, Issue 4

Publisher : FOREX Publication

Published : 30 November 2025

e-ISSN : 2347-470X

Page(s) : 656-664

DOI: https://doi.org/10.37391/IJEER.130404

Abstract

In Very Large-Scale Integration (VLSI) design, minimizing area and optimizing device performance have become paramount as traditional MOSFET scaling approaches fundamental limits. Energy efficiency is now a primary goal due to MOSFET scaling challenges. Multi-valued logic (MVL), such as quaternary (2-bit) logic, offers a potential solution by increasing information density and reducing interconnect complexity. However, implementing four discrete voltage levels in quaternary logic requires novel device technologies. This work explores Spatial Wavefunction Switched FET (SWS-FET) devices – quantum well transistors enabling multi-state carrier transport – as a size- and power-efficient platform for quaternary logic. We present the development of complementary n-channel and p-channel SWS-FETs to encode the four logic states (00, 01, 10, 11). The proposed SWS-FET quaternary logic gate circuits are designed and simulated using an 180nm CMOS-compatible device model. The accuracy of the SWS-FET circuits is verified in Cadence Virtuoso using a combination of the industry-standard BSIM transistor model and an analog behavioral model (ABM) to capture multi-threshold behavior. Circuit simulations of the 2-bit NOR gate demonstrate that using SWS-FETs reduces transistor count by approximately 42% compared to an equivalent CMOS implementation and by up to 68% compared to current-mode MVL designs. These gains are achieved with low power dissipation and competitive switching speeds, highlighting the promise of SWS-FET technology for energy-efficient multi-valued logic design.

Keywords: Multi-valued logic, Quaternary logic, QDC-FET, SWS-FET, NOR gate, Universal quaternary gate.




Bander Saman, Department of Electrical Engineering, Taif University, Taif, Saudi Arabia; Email: saman@tu.edu.sa

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Bander Saman (2025), Design and Simulation of a Quaternary Logic Gate Using a Universal Spatial Wavefunction Switched Field-Effect Transistor NOR Gate. IJEER 13(4), 656-664. DOI: 10.37391/IJEER.130404.