Research Article | ![]()
Design, Stage-Wise Power Loss Evaluation and Real-Time Validation of Totem-Pole Bridgeless Boost Converter Against DBR–Boost PFC Topology
Author(s): Prachi Wadhawan1*, Prateek Nigam2, and Kishor Thakre3
Published In : International Journal of Electrical and Electronics Research (IJEER) Volume 13, Issue 4
Publisher : FOREX Publication
Published : 30 November 2025
e-ISSN : 2347-470X
Page(s) : 679-685
Abstract
Conventional AC–DC power factor correction (PFC) systems typically employ a diode bridge rectifier (DBR) followed by a boost converter, resulting in significant conduction losses due to multiple semiconductor paths. This paper presents a comprehensive design, modeling, and comparative loss analysis of a Totem-Pole Bridgeless Boost Converter (TPBBC) as an efficient alternative to the DBR–Boost configuration. The proposed topology eliminates the front-end diode bridge, reducing conduction and switching losses while improving efficiency and power quality. Detailed MATLAB/Simulink simulations and real-time validation using OPAL-RT demonstrate the superior performance of the Totem-Pole converter, achieving higher efficiency, lower total harmonic distortion (THD), and near-unity power factor. A stage-wise power loss evaluation further confirms reduced device stress and ripple-free DC-link voltage. The results validate the Totem-Pole topology as a high-performance solution for next-generation AC–DC conversion applications requiring enhanced efficiency and power quality.
Keywords: Bridgeless PFC Topology, Stage-wise Loss Breakdown, Voltage Stress Mitigation, Interleaved Totem-Pole Converter, Real-Time HIL Validation.
Prachi Wadhwaan*, Rabindranath Tagore University Bhopal, India; Email: prachibnd22@gmail.com
Prateek Nigam, Rabindranath Tagore University Bhopal, India; Email: prateek.nigam@rntu.ac.in
Kishor Thakre, Rabindranath Tagore University Bhopal, India; Email: kishor.thakre@rntu.ac.in
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