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Research Article |

Low-Power 12T SRAM Design Using 18 nm FinFET Technology

Author(s): Ajaykumar Dharmireddy1*, I. Hemalatha2, B. Veera Kumar3, K.Havella Raj4, and K.Veerannababu5

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 13, Issue 4

Publisher : FOREX Publication

Published : 10 December 2025

e-ISSN : 2347-470X

Page(s) : 697-703

DOI: https://doi.org/10.37391/IJEER.130409

Abstract

This paper presents a low-power and high-stability 12T SRAM cell designed using 18nm FinFET technologies and compared with conventional 6T, 8T, and 10T architectures. The proposed design employs read-path isolation, stacked transistors, and a leakage-controlled sleep mechanism to minimize dynamic and static power while improving read/write stability. Simulations were carried out in Cadence Virtuoso using PTM BSIM-CMG models under varied PVT conditions (0.8–1.0 V, –25 °C to 50 °C). The results show significant enhancements in performance metrics, achieving read SNM of 205 mV, hold SNM of 245 mV, and read/write delays of 52ps and 61ps, respectively. The proposed design demonstrates up to 60% reduction in read power and 28% overall power savings compared with traditional SRAM cells. The layout area of 0.61 µm² corresponds to an array density of 1.64 Mbits/mm², only a 1.25× overhead relative to a 6T cell. Monte Carlo simulations with 200 samples confirmed less than ±10% variation in power, ensuring robust and energy-efficient operation. The proposed 12T FinFET SRAM is thus a strong candidate for next-generation low-power, high-density memory applications in advanced VLSI systems.

Keywords: FinFET, SRAM, 12T memory cell, Static Noise Margin (SNM), Write Margin, Low-power design, Monte Carlo Simulation, Process variation, Read/Write delay, VLSI memory architecture.




Ajaykumar Dharmireddy*, Department of E.C.E, Sir C. R. Reddy College of Engineering, Eluru, Andhra Pradesh, India; Email: ajaykumardharmireddy@sircrrengg.ac.in

I. Hemalatha, Department of E.C.E, Sir C. R. Reddy College of Engineering, Eluru, Andhra Pradesh, India; Email: hema_2024@sircrrengg.ac.in

B. Veera Kumar, Department of E.C.E, Sir C. R. Reddy College of Engineering, Eluru, Andhra Pradesh, India; Email: veerrakumar909@gmail.com

K.Havella Raj, Department of E.C.E, Sir C. R. Reddy College of Engineering, Eluru, Andhra Pradesh, India; Email: haveelaraj.kandavalli@gmail.com

K.Veerannababu, Department of E.C.E, Sir C. R. Reddy College of Engineering, Eluru, Andhra Pradesh, India; Department of E.C.E, Sasi Institute of Technology and Engineering, Tadepalligudem, Andhrapradesh, India; Email: veerannababu.kottu@sasi.ac.in

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Ajaykumar Dharmireddy, I. Hemalatha, B. Veera Kumar, K.Havella Raj, K.Veerannababu (2025), Low-Power 12T SRAM Design Using 18 nm FinFET Technology. IJEER 13(4), 697-703. DOI: 10.37391/IJEER.130409.