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Research Article |

Leakage current analysis for stack based Nano CMOS Digital Circuits

Author(s): Pankaj Agrawal and Nikhil Saxena

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 2, Issue 2

Publisher : FOREX Publication

Published : 30 June 2014

e-ISSN : 2347-470X

Page(s) : 5-11

DOI: https://doi.org/10.37391/IJEER.020202

Abstract

Due to the growing impact of subthreshold and gate leakage, static leakage is contributing more and more towards the power dissipation in deep submicron Nano CMOS technology. There have been many works on subthreshold leakage and techniques to reduce it, such as controlling the input vector to the circuit in standby mode, forcing stack and body bias control. In this tutorial paper we have reviewed the leakage current with change in drain source, gate and bulk voltages for 4 different submicron technologies using the latest PTM models. Simulation result shows the effect of gate leakage and subthreshold leakage in total leakage current for different input vectors for a stack of 3 Nano technology NMOS transistors, further analyzes also the subthreshold and total leakage variation with input vector in a stack of 4 Nano technology NMOS transistors.

Keywords: Leakage Current, Subthreshold Leakage Current, Gate Tunneling Leakage Current, Minimum leakage vector, Digital CMOS Circuit.




Pankaj Agrawal1*, Associate Professor Department of Electronics & Communication IPS College of Technology & Management Gwalior, India; Email: Pankajgate2000@gmail.com

Nikhil Saxena2, Assistant Professor Department of Electronics & Communication Institute of Technology & Management Gwalior, India; Email: axena.nikhil9@gmail.com

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Pankaj Agrawal and Nikhil Saxena (2014), Leakage current analysis for stack based Nano CMOS Digital Circuits. IJEER 2(2), 5-11. DOI: 10.37391/IJEER.020202.