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Research Article |

Comparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits

Author(s): Vikas Agarwal and Shweta Agrawal

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 3, issue 3

Publisher : FOREX Publication

Published : 30 september 2015

e-ISSN : 2347-470X

Page(s) : 66-69

DOI: https://doi.org/10.37391/IJEER.030305

Abstract

In order to increase transmission line stability, control power flow and improve the security of transmission systems FACTS technology has been extensively employed. And these devices must be optimally placed in the transmission systems for their best usage. In this paper to control the congestion in the transmission lines we use DLUF (Disparity Line Utilization Factor) for the appropriate placement of IPFC. The difference between the percentages MVA utilization of each line connected to the same bus is determined by the DLUF. The IPFC is placed in the lines with maximum DLUF. Krill Herd Algorithm has been used for optimal tuning of IPFC for a multi objective function. The multi objective function comprises of minimization of active power loss, security margin, voltage deviation and capacity of installed IPFC. The effectiveness of proposed method is tested for IEEE–30 bus test system.

Keywords: Low Power, Low Leakage, Leakage Power, Power Gating.




Vikas Agarwal*, M.Tech Research Scholar, SRCEM, Gwalior (MP) ; Email: vikas.agarwal38@yahoo.com

Shweta Agrawal, Assistance professor SRCEM, Gwalior (MP); Email: ershwetaagrawal@yahoo.com

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Vikas Agarwal and Shweta Agrawal (2015), Comparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits. IJEER 3(3), 66-69. DOI: 10.37391/IJEER.030305.