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Research Article |

Comparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits

Author(s): Vikas Agarwal and Shweta Agrawal

Publisher : FOREX Publication

Published : 30 september 2015

e-ISSN : 2347-470X

Page(s) : 66-69




Vikas Agarwal*, M.Tech Research Scholar, SRCEM, Gwalior (MP) ; Email: vikas.agarwal38@yahoo.com

Shweta Agrawal, Assistance professor SRCEM, Gwalior (MP); Email: ershwetaagrawal@yahoo.com

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Vikas Agarwal and Shweta Agrawal (2015), Comparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits. IJEER 3(3), 66-69. DOI: 10.37391/IJEER.030305.