FOREX Press I. J. of Electrical & Electronics Research
Support Open Access

Research Article |

Design of Low Power and Process Control Hybrid Adder with Complemented Carry Structure

Author(s): Bhaskara Rao Doddi1, V. Leela Rani2 and G. Rajita3

Publisher : FOREX Publication

Published : 25 December 2022

e-ISSN : 2347-470X

Page(s) : 1239-1246




Bhaskara Rao Doddi*, Department of Electronics and Communication, GIET University, Gunupur, Odisha, India; Email: bhaskararao.doddi@giet.edu

V. Leela Rani, Department of ECE, GVP College of engineering (A), Visakhapatnam, Andhra Pradesh, India; Email: leelarani.vanapalli@gmail.com

G. Rajita, Department of Electronics and Communication, GIET University, Gunupur, Odisha, India; Email: g.rajita@giet.edu

    [1] Chandrakasan, A. P., Sheng, S., and Brodersen, R.W. Low-power CMOS digital design. IEEE journal of solid-state circuits. 1992; 27(4): 473-84. doi=10.1.1.136.1616&rep=rep1&type=pdf[Cross Ref]
    [2] Goel, S., Kumar, A., and Bayoumi, M. Design of robust, energy-efficient full adders for deep- submicrometer design using hybrid-CMOS logic style. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2006; 14(12): 1309-21. doi/10.1109/TVLSI.2006.887807[Cross Ref]
    [3] Aguirre-Hernandez, M., and Linares-Aranda, M. CMOS full-adders for energy-efficient arithmetic applications. IEEE transactions on very large scale integration (VLSI) systems. 2011; 19(4):718-21. doi: 10.1109/TVLSI.2009.2038166[Cross Ref]
    [4] Foroutan, V., Taheri, M., Navi, K., and Mazreah, A. A. Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style. Integration. 2014; 47(1):48-61. doi.org/10.1016/j.vlsi.2013.05.001[Cross Ref]
    [5] Hassoune, I., Flandre, D., O’Connor, I., and Legat, J.D. ULPFA: A new efficient design of a power-aware full adder. IEEE Transactions on Circuits and Systems. I, Reg. Papers. 2010; 57(8):2066-74. doi:10.1109/TCSI.2008.2001367[Cross Ref]
    [6] Agarwal, M., Agrawal, N., and Alam, M. A. A new design of low power high speed hybrid CMOS full adder. In International Conference on Signal Processing and Integrated Networks (SPIN): 1 Feb, 2014; Noida, Delhi, 448-52.doi: 10.1109/SPIN.2014.6776995[Cross Ref]
    [7] Vesterbacka, M. A 14-transistor CMOS full adder with full swing nodes. In Proc. IEEE Workshop on Signal Process. Systems; 22-22 Oct, 1999; Taipei, Taiwan, 713-22. doi: 10.1109/SPIN.2014.6776995[Cross Ref]
    [8] Zhang, M., Gu, J., and Chang, C. H. A novel hybrid pass logic with static CMOS output drive full-adder cell. In Proceedings of the 2003 International Symposium on Circuits and Systems: 25 May, 2003; Nanyang Avenue, Singapore, 317-20. doi: 10.1109/ISCAS.2003.1206266.[Cross Ref]
    [9] Tung, C. K., Shieh, S.H., and Cheng, C. H. Low-power high-speed full adder for portable electronic applications. Electronics Letters. 2013; 49(17): 1063-4. doi.org/10.1049/el.2013.0893[Cross Ref]
    [10] Bhattacharyya, P., Kundu, B., Ghosh, S., Kumar, V., and Dandapat, A. Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. IEEE Transactions on very large-scale integration (VLSI) systems. 2014; 23(10): 2001-8. doi.org/10.1109/TVLSI.2014.2357057[Cross Ref]
    [11] Radhakrishnan, D. Low-voltage low-power CMOS full adder. IEEE Proceedings-Circuits, Devices and Systems. 2001; 148(1): 19-24. doi:10.1049/ip-cds:20010170[Cross Ref]
    [12] Valashani, M. A., and Mirzakuchaki, S. A novel fast, low-power and high-performance XOR-XNOR cell. In 2016 IEEE International Symposium on Circuits and Systems (ISCAS): 1 May, 2016; 694-97. doi.org/10.1109/ISCAS.2016.7527335[Cross Ref]
    [13] Hamed, N., and Somayeh, T. Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates. IEEE transactions on very large-scale integration (VLSI) systems. 2018; 26(8):1-13. doi:10.1109/TVLSI.2018.2820999[Cross Ref]
    [14] Kandpal, J., Tomar, A., Agarwal, M., and Sharma, K.K. High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell. IEEE transactions on VLSI systems. 2020; 28(6):1413-22. doi: 10.1109/TVLSI.2020.298385.[Cross Ref]
    [15] Hasan, M., Hossein, M.J., Hossain, M., Zaman, H.U., and Islam, S. Design of a scalable Low-Power 1-bit Hybrid Full adder for fast computation. IEEE transactions on circuits and systems -II: Express briefs. 2020; 67(8): 1464-68. doi: 10.1109/TCSII.2019.2940558[Cross Ref]
    [16] Kumar, P., and Sharma, R.K. Low voltage high performance hybrid full adder. Engineering Science and Technology, an International Journal. 2016; 19(1):559-65.[Cross Ref]
    [17] Shams, A.M., Darwish, T.K., and Bayoumi, M. Performance analysis of low-power 1-bit CMOS full adder cells. IEEE transactions on very large scale integration VLSI systems. 2002; 10(1): 20-29. doi: 10.1109/92.988727[Cross Ref]
    [18] Goel, S., Elgamel, M., Bayoumi, M., and Hanafy, Y. Design methodologies for high-performance noise-tolerant XOR-XNOR circuits. IEEE Transactions on Circuits and Systems I: regular papers.2006; 53(4):867-78. doi=10.1.1.1080.9120&rep=rep1&type=pdf[Cross Ref]
    [19] Shams, A.M., and Bayoumi, M.A. A novel high-performance CMOS 1-bit full-adder cell. IEEE Transactions on Circuits and Systems II. Analog Digit. Signal Process. 2000; 47(5):478-81. doi: 10.1109/82.842117.[Cross Ref]
    [20] Alioto, M. and Palumbo, G. Analysis and comparison on full adder block in submicron technology. IEEE transactions on very large scale integration VLSI systems. 2002; 10(6): 806-23. doi=10.1.1.105.2917&rep=rep1&type=pdf[Cross Ref]
    [21] Parameshwara, M.C., and Srinivasaiah, H.C. Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications. Journal of Circuits, Systems, and Computers. 2016; 26(1):1-15. doi.org/10.1142/S0218126617500141.[Cross Ref]
    [22] Shahbaz, H., Mehedi, H., Gazal, A. and Mohd, H. A high- performance full swing 1-bit hybrid full adder cell. IET Circuits Devices & Systems. 2021; 16(3): 210-17. doi.org/10.1049/cds2.12097.[Cross Ref]
    [23] Kandpal, J., Tomar, A., and Agarwal, M. Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications. Microelectronics Journal, 2021; 115(5): doi:10.1016/j.mejo.2021.105205.[Cross Ref]
    [24] Mehedi, H., Md. Shahbaz, H., Mainul, H., Mohd, H., Hasan,. Z., and Sharnali, I. High-speed and scalable XOR-XNOR-based hybrid full adder design. Computers and Electrical Engineering, 2021; 93(1): doi.org/10.1016/j.compeleceng.2021.107200.[Cross Ref]

Bhaskara Rao Doddi, V. Leela Rani and G. Rajita (2022), Design of Low Power and Process Control Hybrid Adder with Complemented Carry Structure. IJEER 10(4), 1239-1246. DOI: 10.37391/IJEER.100475.