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Research Article |

Design and Characterization of a Novel FinFET based NCL Cell Library for High Performance Asynchronous Circuits

Author(s): Jayesh Diwan 1*, Nagendra Gajjar2

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 11, Issue 1,  

Publisher : FOREX Publication

Published : 20 February 2023

e-ISSN : 2347-470X

Page(s) : 84-89

DOI: https://doi.org/10.37391/IJEER.110111

Abstract

In recent times, synchronous circuits are facing design related issues like clock skew, glitch power, EMI, leakage power, etc. The clock-less design paradigm – Asynchronous design challenges most of these issues and accepted as a better alternative to clocked circuits. QDI based Null Convention Logic (NCL) is such a clock-less design concept. However, NCL designs couldn’t get wide spread acceptance due to unavailability of commercial CAD tools and design compatible NCL standard cell library. The proposed research work in this paper demonstrates design and characterization of FinFET based NCL cell library to facilitate QDI based asynchronous circuit design. The NCL cells are designed with ASAP 7nm PDK. A complete set of 27 NCL threshold gates are developed and characterized in cadence using ocean scripting. Various time and energy models are extracted for different process corners using EDA platform. The proposed work will help research scholars to implement NCL based asynchronous circuits. This paper also demonstrates comparative performance analysis of bulk-CMOS and multi-gate FinFET based NCL threshold gates in 16 nanometer technology. The analysis has concluded average 19% of improvement in power-delay produce for FinFET based cells compared to its CMOS counterparts. To showcase two-dimensional comparison, various static and semi-static NCL gate structures are also compared in term of their power and speed. Various arithmetic circuits are designed using these standard NCL cells to demonstrate its application. The results indicated substantial performance improvement in terms of power and speed.

Keywords: Clock-less Design, Null Convention Logic, Delay-Insensitive circuits, Multi-gate devices




Jayesh Diwan*, Research Scholar, EC Department, Nirma University, Ahmedabad, Gujarat, India; Email: jayeshdiwan@gmail.com

Nagendra Gajjar, Professor (Ph.D), EC Department, Nirma University, Ahmedabad, Gujarat, India; Email: nagendra.gajjar@nirmauni.ac.in

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Jayesh Diwan and Nagendra Gajjar (2023), Design and Characterization of a Novel FinFET based NCL Cell Library for High Performance Asynchronous Circuits . IJEER 11(1), 84-89. DOI: 10.37391/IJEER.110111.