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Research Article |

Communication Latency and Power Consumption Consequence in Multi-Core Architectures and Improvement Methods

Author(s): Venkata Sridhar .T1* and G. Chenchu Krishnaiah2

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 11, Issue 1

Publisher : FOREX Publication

Published : 30 March 2023

e-ISSN : 2347-470X

Page(s) : 222-227

DOI: https://doi.org/10.37391/IJEER.110130

Abstract

The present electronics world has a lot of dependency on processing devices in the current and future developments. Even non-electronic industries have much data to process and are indirectly dependent on processors. The larger the number of processors incorporated into the architecture, will lower the data handling and processing time; thus, efficiency improves. Hence multi-core processors have become a regular part of the design of processing elements in the electronic industry. The large number of processors incorporated into the system architecture results in difficulty in communicating among them without a deadlock or live lock. NoC is a promising solution for communicating among the on-chip processors, provided it is fast enough and consumes less energy. Further, the latency among the multi-core processors should be optimal to stand with the increasing data acquisition and processing in the new/developing operating systems and software. This paper addresses energy efficiency and latency reduction methods/techniques for Multi-core architectures.

Keywords: Latency, NoC (Network on Chip), NoC Router, Multi-core SoCs(System on Chips)




Venkata Sridhar .T*, Department of Electronics and Communication, VTU, Belgaum, India; Email: venkatasridhar.thatiparthi@gmail.com; Department of ETC, IIIT-Bhubaneswar, Bhubaneswar, India; Email: venkatasridhar@iiit-bh.ac.in

G. Chenchu Krishnaiah, Department of ECE, ASCET, Gudur, India; Email: gurramchenchukrishnaiah@gmail.com

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Venkata Sridhar. T and G. Chenchu Krishnaiah (2023), Communication Latency and Power Consumption Consequence in Multi-Core Architectures and Improvement Methods. IJEER 11(1), 222-227. DOI: 10.37391/IJEER.110130.