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Research Article |

Multiplication free Fast-Adaptive Binary Range Coder using ISW

Author(s): Sunkara Teena Mrudula1*, K.E. Srinivasa Murthy2 and M.N. Giri Prasad3

Published In : International Journal of Electrical and Electronics Research (IJEER)        Volume 11, Issue 1

Publisher : FOREX Publication

Published : 30 March 2023

e-ISSN : 2347-470X

Page(s) : 228-235

DOI: https://doi.org/10.37391/IJEER.110131

Abstract

Data compression is defined as the process of encoding, converting and modifying the bits-structures of data in such a way that reduces less-spaces on the disk. Fast-ABRC, a new context ABRC for compressing the image and video. This paper introduces novel hardware F-ABRC (Fast-adaptive binary range coder) and architecture of VLSI, as it doesn’t have requirement of LUTs (Look-up-Tables) and also it is completely multiplication free. To get the result, we will combine the utilization of simple operation to compute the approximation after encoding every single symbol and the PE (probability estimation) on the basis of ISW (Imaginary Sliding Window) with approximation of the multiplication. We have represented our introduced algorithm, which is faster and in comparison, to the existing model it gives superior compression efficiency and the comparison takes place on the basis of two parameters such as power dissipation (Dynamic and Static) and device utilization.

Keywords: F-ABRC, ISW, VLSI




Sunkara Teena Mrudula*, Research Scholar, Dept of ECE, Jawaharlal Nehru Technological University Anantapur, Anantapuramu 515002, A.P, India; Email: sunkaramrudula@gmail.com

K.E. Srinivasa Murthy, Professor, Department of ECE, Ravindra College of Engineering for Women, Kurnool, A.P, India

M.N. Giri Prasad, Professor, Jawaharlal Nehru Technological University Anantapur, Anantapuramu 515002, A.P, India

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Sunkara Teena Mrudula, K.E. Srinivasa Murthy and M.N. Giri Prasad (2023), Multiplication free Fast-Adaptive Binary Range Coder using ISW. IJEER 11(1), 228-235. DOI: 10.37391/IJEER.110131.